参数资料
| 型号： | NCP5220MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/18页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL BUCK PWR 20-DFN |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFDFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（6x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5220MNR2GOSCT |
NCP5220
DETAILED OPERATION DESCRIPTIONS
General
The NCP5220 3?in?1 PWM Dual Buck Linear DDR
Power Controller contains two high efficiency PWM
controllers and an integrated two?quadrant linear regulator.
The VDDQ supply is produced by a PWM switching
controller with two external N?Ch FETs. The VTT
termination voltage is an integrated linear regulator with
sourcing and sinking current capability which tracks at ?
VDDQ. The MCH core voltage is created by the secondary
switching controller.
The inclusion of soft?start, supply undervoltage monitors
and thermal shutdown, makes this device a total power
solution for the MCH and DDR memory system. This device
is packaged in a DFN?20.
ACPI Control Logic
The ACPI control logic is powered by the 5VDUAL
supply. It accepts external control at the SLP_S3 input and
internal supply voltage monitoring signals from two
UVLOs to decode the operating mode in accordance with
the state transition diagram in Figure 18.
These UVLOs monitor the external supplies, 5VDUAL
and 12VATX, through 5VDUAL and BOOT pins
respectively. Two control signals, _5VDUALGD and
_BOOTGD, are asserted when the supply voltages are good.
When the device is powered up initially, it is in the S5
shutdown mode to minimize the power consumption. When
all three supply voltages are good with SLP_S3 and SLP_S5
remaining HIGH, the device enters the S0 normal operating
mode. The transition of SLP_S3 from HIGH to LOW while
in the S0 mode, triggers the device into the S3 sleep mode.
In S3 mode the 12VATX supply collapses. On transition of
SLP_S3 from LOW to HIGH, the device returns to S0 mode.
The IC can re?enter S5 mode by setting SLP_S5 LOW. A
timing diagram is shown in Figure 17.
Table 1 summarizes the operating states of all the
regulators, as well as the conditions of the output pins.
Internal Bandgap Voltage Reference
An internal bandgap reference is generated whenever
5VDUAL exceeds 2.7 V. Once this bandgap reference is in
regulation, an internal signal _VREFGD will be asserted.
Table 1. Mode, Operation and Output Pin Conditions
OPERATING CONDITIONS
S5 to S0 Mode Power?Up Sequence
The ACPI control logic is enabled by the assertion of
_VREFGD. Once the ACPI control is activated, the power?
up sequence starts by waking up the 5VDUAL voltage
monitor block. If the 5VDUAL supply is within the preset
levels, the BOOT undervoltage monitor block is then
enabled. After 12VATX is ready and the BOOT UVLO is
asserted LOW, the ACPI control triggers this device from S5
shutdown mode into S0 normal operating mode by
activating the soft?start of DDQ switching regulator,
providing SLP_S3 and SLP_S5 remain HIGH.
Once the DDQ regulator is in regulation and the soft?start
interval is completed, the _InRegDDQ signal is asserted
HIGH to enable the VTT regulator as well as the V1P5
switching regulator.
DDQ Switching Regulator
In S0 mode the DDQ regulator is a switching synchronous
rectification buck controller driving two external power
N?Ch FETs to supply up to 20 A. It employs voltage mode
fixed frequency PWM control with external compensation
switching at 250kHz ± 13.2%. As shown in Figure 2, the
VDDQ output voltage is divided down and fed back to the
inverting input of an internal amplifier through the FBDDQ
pin to close the loop at VDDQ = VFBQ × (1 + R1/R2). This
amplifier compares the feedback voltage with an internal
reference voltage of 1.190 V to generate an error signal for
the PWM comparator. This error signal is compared with a
fixed frequency RAMP waveform derived from the internal
oscillator to generate a pulse?width?modulated signal. This
PWM signal drives the external N?Ch FETs via the
TG_DDQ and BG_DDQ pins. External inductor L and
capacitor COUT1 filter the output waveform. When the IC
leaves the S5 state, the VDDQ output voltage ramps up at a
soft?start rate controlled by the capacitor at the SS pin.
When the regulation of VDDQ is detected in S0 mode,
_INREGDDQ goes HIGH to notify the control block.
In S3 standby mode, the switching frequency is doubled
to reduce the conduction loss in the external N?Ch FETs.
OUTPUT PIN CONDITIONS
MODE
S0
S3
S5
DDQ
Normal
Standby
OFF
VTT
Normal
H?Z
H?Z
MCH
Normal
OFF
OFF
TG_DDQ
Normal
Standby
Low
BG_DDQ
Normal
Standby
Low
TP_1P5
Normal
Low
Low
BG_1P5
Normal
Low
Low
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