参数资料
| 型号： | NCP5220MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL BUCK PWR 20-DFN |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFDFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（6x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5220MNR2GOSCT |
NCP5220
APPLICATION INFORMATION
Application Circuit
Figure 20, on the following page, shows the typical
application circuit for NCP5220. The NCP5220 is
specifically designed as a total power solution for the MCH
and DDR memory system. This diagram contains NCP5220
for driving four external N?Ch FETs to form the DDR
memory supply voltage (VDDQ) and the MCH regulator.
Output Inductor Selection
The value of the output inductor is chosen by balancing
ripple current with transient response capability. A value of
1.7 m H will yield about 3.0 A peak?peak ripple current when
converting from 5.0 V to 2.5 V at 250 kHz. It is important
that the rated inductor current is not exceeded during full
load, and that the saturation current is not less than the
expected peak current. Low ESR inductors may be required
to minimize DC losses and temperature rise.
Input Capacitor Selection
Input capacitors for PWM power supplies are required to
provide a stable, low impedance source node for the buck
regulator to convert from. The usual practice is to use a
combination of electrolytic capacitors and multi?layer
ceramic capacitors to provide bulk capacitance and high
frequency noise suppression. It is important that the
capacitors are rated to handle the AC ripple current at the
input of the buck regulators, as well as the input voltage. In
the NCP5220 the DDQ and MCH regulators are interleaved
(out of phase by 180 degrees) to reduce the peak AC input
current.
Output Capacitor Selection
Output capacitors are chosen by balancing the cost with
the requirements for low output ripple voltage and transient
voltage. Low ESR electrolytic capacitors can be effective at
reducing ripple voltage at 250 kHz. Low ESR ceramic
capacitors are most effective at reducing output voltage
excursions caused by fast load steps of system memory and
the memory controller.
12VATX
TP2
D2
BAT54HT1
D2
Power MOSFET Selection
Power MOSFETs are chosen by balancing the cost with
the requirements for the current load of the memory system
and the efficiency of the converter provided. The selections
criteria can be based on drain?source voltage, drain current,
on?resistance R DS(on) and input gate capacitance. Low
R DS(on) and high drain current power MOSFETs are usually
preferred to achieve the high current requirement of the
DDR memory system and MCH, as well as the high
efficiency of the converter. The tradeoff is a corresponding
increase in the input gate capacitor of the power MOSFETs.
PCB Layout Considerations
With careful PCB layout the NCP5220 can supply 20 A or
more of current. It is very important to use wide traces or
large copper shapes to carry current from the input node
through the MOSFET switches, inductor and to the output
filters and load. Reducing the length of high current nodes
will reduce losses and reduce parasitic inductance. It is
usually best to locate the input capacitors the MOSFET
switches and the output inductor in close proximity to
reduce DC losses, parasitic inductance losses and radiated
EMI.
The sensitive voltage feedback and compensation
networks should be placed near the NCP5220 and away
from the switch nodes and other noisy circuit elements.
Placing compensation components near each other will
minimize the loop area and further reduce noise
susceptibility.
Optional Boost Voltage Configuration
The charge pump circuit in Figure 19 can be used instead
of boost voltage scheme of Figure 20. The advantage in
Figure 19 is the elimination of the requirement for the Zener
clamp.
5VDUAL
TP2
D1
BAT54HT1
NCP5220
BAT54HT1
SW_DDQ 20
BG_DDQ 19
TG_DDQ 18
BOOT 17
5VDUAL 16
5VDUAL
R2
4.7 1
R3
1k
4
Q2
3 NTD40N03
C4
100 nF
L
VDDQ
TP5
15
12
COMP_1P5
SLP_S3 14
TG_1P5 13
BG_1P5
R4
4.7
1
4 DPAK
Q2
NTD40N03
3
C6
4.7
m F
+
C7
2200
m F
+
C25
2200
m F
R15 2.5 VDDQ
1k
GND_1P5
11
Figure 19. Charge Pump Circuit at BOOT Pin
http://onsemi.com
14
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