参数资料
| 型号： | NCP5220MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/18页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL BUCK PWR 20-DFN |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFDFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（6x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5220MNR2GOSCT |
NCP5220
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive non?overlap timing control of the complementary
gate drive output signals is provided to reduce
shoot?through current that degrades efficiency.
Tolerance of VDDQ
Both the tolerance of VFBQ and the ratio of the external
resistor divider R1/R2 impact the precision of VDDQ. With
the control loop in regulation, VDDQ = VFBQ × (1 +
R1/R2). With a worst case (for all valid operating
conditions) VFBQ tolerance of ± 1.5%, a worst case range of
± 2% for VDDQ will be assured if the ratio R1/R2 is
specified as 1.100 ± 1%.
Fault Protection of VDDQ Regulator
In S0 mode, an internal voltage (VOCP) = 5VDUAL – 0.8
sets the current limit for the high?side switch. The voltage
VOCP pin is compared to the voltage at SWDDQ pin when
the high?side gate drive is turned on after a fixed period of
blanking time to avoid false current limit triggering. When
the voltage at SWDDQ is lower than VOCP, an overcurrent
condition occurs and all regulators are latched off to protect
against overcurrent. The IC will be powered up again if one
of the supply voltages, 5VDUAL, SLP_S5 or 12VATX, is
recycled. The main purpose is for fault protection, not for
precise current limit.
In S3 mode, this overcurrent protection feature is
disabled.
Feedback Compensation of VDDQ Regulator
The compensation network is shown in Figure 2.
VTT Active Terminator
The VTT active terminator is a 2 quadrant linear regulator
with two internal N?Ch FETs to provide current sink and
source capability up to 2.0 A. It is activated only when the
DDQ regulator is in regulation in S0 mode. It draws power
from VDDQ with the internal gate drive power derived from
5VDUAL. While VTT output is connecting to the FBVTT
pin directly, VTT voltage is designed to automatically track
at the half of VDDQ. This regulator is stable with any value
of output capacitor greater than 470 m F, and is insensitive to
ESR ranging from 1 m W to 400 m W .
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, bi?directional
current limit preset at 2.4 A magnitude is implemented. The
VTT provides a soft?start function during start up.
MCH Switching Regulator
The secondary switching regulator is identical to the DDQ
regulator except the output is 10 A. No fault protection is
implemented and the soft?start timing is twice as fast with
respect to CSS.
BOOT Pin Supply Voltage
In typical application, a flying capacitor is connected
between SWDDQ and BOOT pins. In S0 mode, 12VATX is
tied to BOOT pin through a Schottky diode as well. A 13 V
Zener clamp circuit must clamp this boot strapping voltage
produced by the flying capacitor in S0 mode.
In S3 mode the 12VATX is collapsed and the BOOT
voltage is created by the Schottky diode between 5VDUAL
and BOOT pins as well as the flying capacitor. The
BOOT_UVLO works specially. The _BOOTGD goes low
and the IC remains in S3 mode.
Thermal Consideration
Assuming an ambient temperature of 50 ° C, the maximum
allowed dissipated power of DFN?20 is 2.8 W, which is
enough to handle the internal power dissipation in S0 mode.
To take full advantage of the thermal capability of this
package, the exposed pad underneath must be soldered
directly onto a PCB metal substrate to allow good
thermal contact.
Thermal Shutdown
When the junction temperature of the IC exceeds 145 ° C,
the entire IC is shutdown. When the junction temperature
drops below 120 ° C, the chip resumes normal operation.
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