参数资料
| 型号： | NCP5220MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL BUCK PWR 20-DFN |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFDFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（6x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5220MNR2GOSCT |
NCP5220
5VSTBY
or
5VDUAL
12 V
SLP_S5
SLP_S3
SS Pin
DDQ?S0
VTT
MCH
Switching
Frequency
Doubles
State
1
2
3
4
5
6
7
8
9
10
11 12 13
14
15 16
17
SO
S3
SO
S5
2. 5VSTBY or 5VSTB is the ultimate chip enable, SLP_S5 and SLP_S3 go HIGH. This supply has to be up first to
ensure gates are in known state.
3. 12 V supply ramp.
4. DDQ will ramp with the tracking of SS pin, timing is 1.2 * C SS / 4 m (sec).
5. DDQ SS is completed, then SS pin is released from DDQ. SS pin is shorted to ground.
5. MCH ramps with the tracking of SS pin ramp, timing is 0.8 * C SS / 8 m (sec). VTT start up with current limit.
6. MCH SS is completed, then SS pin is released from MCH, SS pin is shorted to ground. S0 Mode.
7. S3 MODE ?? SLP_S3 = L.
8. VTT and MCH will be turned off.
9. 12 V ramps to 0 V.
10. Standar d S3 State.
11. SLP_S3 goes HIGH.
12. 12 V ramps back to regulation.
13. 12 V UVLO = L and SLP_S3 = H. MCH ramps with SS pin, timing is 0.8 * C SS / 8 m (sec). VTT rises.
14. S0 Mode.
15. S5 Mode ?? SLP_S5 = L.
16. DDQ, VTT and MCH Turned OFF.
17. S5 Mode.
Figure 17. NCP5220 Power?Up and Power?Down
http://onsemi.com
12
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