参数资料
型号: NCP5322ADW
厂商: ON Semiconductor
文件页数: 20/31页
文件大小: 0K
描述: IC CTLR BUCK 2PH DRVR/DAC 28SOIC
产品变化通告: Product Obsolescence 11/Feb/2009
标准包装: 26
应用: 控制器,高性能处理器
输入电压: 4.5 V ~ 14 V
输出数: 2
输出电压: 3.3V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC
包装: 管件
NCP5322A
current (I O,MAX ), the per capacitor ESR of the output
VOUT,FULL?LOAD +
(14)
capacitors (ESR OUT ), and the number of the output
capacitors (N OUT ) as shown in Figure 16. Assuming the load
current is shared equally between the two phases, the output
voltage at full, transient load will be:
MAX dI/dt occurs in
first few PWM cycles.
VOUT,NO?LOAD * (IO,MAX 2) @ ESROUT NOUT
V OUT
I Li
Vi(t = 0) = 12 V
Q1
SWNODE
I Lo
Vo(t = 0) = 1.630 V
Li
TBD
Lo
700 nH
+ Vi
? 12 V
Ci
3 × 16SP270
ESR Ci
18 m/3 = 6.0 m
+ V Ci
Q2
+ Co
7 × 16MBZ1500M10X20
22.5 u(t)
ESR Co
13 m/7 = 1.9 m
Figure 16. Calculating the Input Inductance
When the control MOSFET (Q1 in Figure 16) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
LiMIN + VLi
+ D VCi
dIIN dtMAX
dIIN dtMAX
(18)
voltage across the output inductor can be calculated as:
dI IN /dt MAX is the maximum allowable input current slew
D VLo + VIN * VOUT,FULL?LOAD
+ VIN * VOUT,NO?LOAD
) (IO,MAX 2) @ ESROUT NOUT
(15)
rate.
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
dILo dt + D VLo Lo
(16)
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors ( D V Ci ) is determined by the number of input
capacitors (N IN ), their per capacitor ESR (ESR IN ), and the
current in the output inductor according to:
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the ?26 or ?52 from Micrometals, the inductance “swing”
with DC bias must be taken into account ? inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
D VCi + ESRIN NIN @ dILo dt @ tON
(17)
minimum value or the dI/dt will be higher than expected.
+ ESRIN NIN @ dILo dt @ D fSW
Before the load is applied, the voltage across the input
inductor (V Li ) is very small ? the input capacitors charge to
the input voltage, V IN . After the load is applied the voltage
drop across the input capacitors, D V Ci , appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
5. MOSFET & Heatsink Selection
Power dissipation, package size, and thermal solution
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
http://onsemi.com
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