参数资料
| 型号： | NCP5332ADW |
| 厂商： | ON Semiconductor |
| 文件页数： | 26/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 2PH DRVR/DAC 28SOIC |
| 产品变化通告： | Product Obsolescence 30/Sept/2009 |
| 标准包装： | 26 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
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NCP5332A
3. Input Capacitor Selection
Use Equation 5 to determine the average input current to
the converter at full?load;
IIN,AVG + IO,MAX @ D h
(5)
+ 45 A @ (1.565 V 12 V) 0.81 + 7.25 A
Next, use Equations 6 to 10 with the full?load inductance
value of 770 nH:
D ILo + (VIN * VOUT) @ D (Lo @ fSW)
+ (12 V * 1.565 V) @
+ 8.03 App
(1.565 V 12 V)
(770 nH @ 220 kHz)
(10)
ILo,MAX + IO,MAX 2 ) D ILo 2
+ 45 A 2 ) 8.03 App 2 + 26.5 A
ILo,MIN + IO,MAX 2 * D ILo 2
+ 45 A 2 * 8.03 App 2 + 18.5 A
IC,MAX + ILo,MAX h * IIN,AVG
+ 26.5 A 0.81 * 7.25 A + 25.5 A
(8)
(9)
(6)
Figure 27. Actual DC/DC Converter Circuitry With the
Calculated Input Inductor and Minimum Filtering
Components. The Measured Slew?Rate (dI IN /dt) of
the Input Current (0.064 A/ m s) Is Much Lower Than
Expected (0.1 A/ m s) Because of Input Voltage Drop,
Parasitic Inductance, and Lower Real ESRs Than
Specified in the Capacitors’ Data Sheets.
First, use Equation 15 to calculate the voltage across the
output inductor due to the 45 A load current being shared
equally between the two phases:
IC,MIN + ILo,MIN h * IIN,AVG
+ 18.5 A 0.81 * 7.25 A + 15.6 A
(7)
D VLo + VIN * VOUT,NO?LOAD
) (IO,MAX 2) @ ESROUT NOUT
(15)
For the two?phase converter, the input capacitor(s) RMS
current at full?load is then (Note: D = 1.565 V/12 V = 0.13):
+ 12 V * 1.85 V ) 45 A 2 @ 13 m W 7
+ 10.19 V
ICIN,RMS + [2D @ (IC,MIN2 ) IC,MIN @ D IC,IN
(11)
Second, use Equation 16 to determine the rate of current
) D IC,IN2 3) ) IIN,AVG2 @ (1 * 2D)]1 2
increase in the output inductor when the load is first applied
(i.e. Lo has not changed much due to the DC current):
+ [0.26 @ (15.62 ) 15.6 @ 8.00 ) 8.002 3)
dILo dt + D VLo Lo
(16)
) 7.252 @ (1 * 0.26)]1 2
+ 11.8 ARMS
+ 10.19 V 1.1 m H + 9.26 V m s
Finally, use Equations 17 and 18 to calculate the minimum
input inductance value:
At this point, the designer must decide between saving
board space by using higher?rated/more costly capacitors or
saving cost by using more lower?rated/less costly
capacitors. To save board space, we choose the SP (Oscon)
series capacitors by Sanyo. Part number 16SP270: 270 μ F,
16 V, 4.4 A RMS , 18 m ? , 10 × 10.5 mm. This design will
require 11.8 A/4.4 A = 2.7 or N IN = 3 capacitors on the input
D VCi + ESRIN NIN @ dILo dt @ D fSW
+ 18 m W 3 @ 9.26 V m s @ 0.157 220 kHz
+ 39.7 mV
LiMIN + D VCi dIIN dtMAX
+ 39.7 mV 0.50 A m s + 80 nH
(17)
(18)
for a conservative design.
4. Input Inductor Selection
The input inductor must limit the input current slew rate
to less than 0.5 A/ μ s during a load transient from 0 to 45 A.
A conservative value will be calculated assuming the
minimum number of output capacitors (N OUT = 7), three
input capacitors (N IN = 3), worst case ESR values for both
the input and output capacitors, and a maximum duty cycle
(D = (1.850 V + 30 mV AVP )/12.0 V IN = 0.157).
Next, choose the small, cost effective T30?26 core from
Micrometals (33.5 nH/N 2 ) with #16 AWG. The design
requires only 1.54 turns to achieve the minimum inductance
value. Allow for inductance “swing” at full?load by using
three turns. The input inductor ’s value will be:
Li + 32 @ 33.5 nH N2 + 301 nH
This inductor is available as part number CTX15?14771
from Coiltronics.
http://onsemi.com
26
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