参数资料
| 型号： | NCP5332ADW |
| 厂商： | ON Semiconductor |
| 文件页数： | 28/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 2PH DRVR/DAC 28SOIC |
| 产品变化通告： | Product Obsolescence 30/Sept/2009 |
| 标准包装： | 26 |
| 应用： | 控制器，高性能处理器 |
| 输入电压： | 4.5 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
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NCP5332A
RDRP +
D VDRP
( D VOUT,FULL?LOAD RVFBK * IBIASVFB)
(31)
9. Current Limit Setting
The maximum inductor resistance, the maximum PCB
+ 227 mV (95 mV 2.0 k W * 15 m A)
+ 6.98 k W
7. Current Sensing
Choose the current sense network (R CSn , C CSn , n = 1 or 2)
to satisfy:
resistance, and the maximum current?sense gain as shown
in Equation 34 determine the current limit. The maximum
current, I OUT,LIM , was specified in the design requirements.
The maximum inductor resistance occurs at full?load and
the highest ambient temperature. This value was found in the
“Output Inductor Selection” (1.33 m ? ). This analysis
assumes the PCB resistance only increases due to the change
RCSn @ CCSn + Lo (RL ) RPCB)
(32)
in ambient temperature. Component heating will also
increase the PCB temperature but quantifying this effect is
Equation 32 will be most accurate for better iron powder
core material (such as the ?8 from Micrometals). This
material is very consistent with DC current and frequency.
Less expensive core materials (such as the ?52 from
Micrometals) change their characteristics with DC current,
AC flux density, and frequency. This material will yield
acceptable converter performance if the current sense time
constant is set lower (longer) than anticipated. As a rule of
thumb, use approximately twice the resistance (R CSn ) or
twice the capacitance (C CSn ) when using the less expensive
core material.
The component values determined thus far are Lo = 1.1 μ H,
R L = 1.03 m ? , and R PCB = 0.50m ? . We choose a convenient
value for C CS1 (0.01 μ F) and solve for R CS1 ;
RCSn + 1.1 m H (1.03 m W ) 0.50 m W ) 0.01 m F
+ 71 k W
Equation 32 will be most accurate for higher quality iron
powder core materials such as the ?2 or ?8 from
Micrometals. The permeability of these more expensive
cores is relatively constant versus DC current, AC flux
density and frequency. Less expensive core materials (such
difficult. Lab testing should be used to “fine tune” the
overcurrent threshold.
RPCB,MAX + 0.50 m W @ (1 ) 0.39% ° C @ (60 * 25) ° C)
+ 0.57 m W
VILIM + (IOUT,LIM ) D ILo 2) @ (RLMAX ) RPCB,MAX)
@ GILIM @ GCSA
+ (52 A ) 8.03 A 2) @ (1.33 m W ) 0.57 m W )
@ 1.93 V V @ 3.50 V V
+ 0.718 Vdc
Set the voltage at the I LIM pin using a resistor divider from
the 3.3 V reference output as shown in Figure 28. If the
resistor from I LIM to GND is chosen as 1 k (R LIM2 ), the
resistor from I LIM to 3.3 V can be calculated from:
RLIM1 + (VREF * VILIM) (VILIM RLIM2)
+ (3.3 V * 0.718 V) (0.718 V 1 k W )
+ 3596 W or 3.57 k W
as the ?52 from Micrometals) change their characteristics
versus DC current, AC flux density, and frequency. The less
expensive materials may yield acceptable converter
3.3 V REF
R LIM1
V LIM
To I LIM Pin
performance if the current sense time constant is set
approximately 1 × ?2 × longer than anticipated. For example,
use up to twice the resistance (R CSn ) or twice the capacitance
(C CSn ) when using the less expensive core material. If we
use ?52 material for this design, the value of R CSn may need
to be increased to 2 × 71 k ? or 142 k ? .
After the circuit is constructed, the values of R CSn and/or
C CSn should be tuned to provide a “square?wave” at V DRP
with minimal overshoot and fast rise time due to a step
change in load current as shown in Figures 20?22.
8. Error Amplifier Tuning
The error amplifier is tuned by adjusting C AMP to provide
an acceptable full?load transient response as shown in
Figures 23?25. After a value for C AMP is chosen, the
peak?to?peak voltage ripple on the COMP pin is examined
R LIM2
1k
Figure 28. Setting the Current Limit
10. PWM Comparator Input Voltage
Use Equation 35 to check the voltage level to the positive
pin of the internal PWM comparators. The design should not
saturate the PWM comparator at maximum DAC output
voltage (+1% error), AVP at full?load, 100% duty cycle (D
= 1), and worst?case maximum internal ramp (310 mV at
100% duty cycle):
VCSREF,MAX + Max VID Setting w AVP @ Full?Load
+ 1.01 @ 1.850 V * 30 mV + 1.834 V
under full?load to insure less than 20 mV PP as shown in
Figure 26.
http://onsemi.com
28
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