参数资料
| 型号： | NCP5380AMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 22/28页 |
| 文件大小： | 0K |
| 描述： | IC CTLR SYNC BUCK SGL 32QFN |
| 标准包装： | 5,000 |
| 应用： | 控制器，Intel VR11 |
| 输入电压： | 5V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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NCP5380, NCP5380A
R O 2
L X v C Z
physical limit is twenty 0805 ? size pieces inside the socket.
Additional ceramic capacitors can be placed along the outer
edge of the socket. A combined ceramic capacitor value of
40 m F to 50 m F is recommended and is usually composed of
multiple 10 m F or 22 m F capacitors.
Ensure that the total amount of bulk capacitance (C X ) is
within its limits. The upper limit is dependent on the VID
OTF output voltage stepping (voltage step, V V , in time, t V ,
with error of V ERR ); the lower limit is based on meeting the
critical capacitance for load release at a given maximum load
step, D I O . The current version of the VR11 specification
allows a maximum V CC overshoot (V OSMAX ) of 10 mV
more than the VID voltage for a step ? off load current.
Ensure that the ESL of the bulk capacitors (L X ) is low
enough to limit the high frequency ringing during a load
change. This is tested using:
Q 2 (eq. 15)
L X v 44 m F (5.1 m W ) 2 2 + 2.3 nH
Where:
Q is limited to the square root of 2 to ensure a critically
damped system.
L X is about 450 pH for the two SP capacitors, which is low
enough to avoid ringing during a load change. If the L X of
the chosen bulk capacitor bank is too large, the number of
ceramic capacitors may need to be increased to prevent
excessive ringing.
D I O
OSMAX
O
C x(MIN) w
C x(MAX) v
k 2
R O )
L
R O 2
L
V
D I
V V
V VID
V VID
* C z
(eq. 13)
(eq. 14)
For this multimode control technique, an all ceramic
capacitor design can be used if the conditions of
Equations 13, 14, and 15 are satisfied.
POWER MOSFETS
For typical 15 A applications, the N ? channel power
MOSFETs are selected for one high ? side switch and two
k
R O
V VID
V V
1 ) t v * 1 * C Z
5.1 m W ) 1.174 V
I O
I R
P SF + (1 * D) ) 1 R DS SF
I R +
C X(MAX ) v
2
L
V ERR
Where k + ? ln
V V
To meet the conditions of these expressions and the
transient response, the ESR of the bulk capacitor bank (R X )
should be less than two times the droop resistance, R O . If the
C X(MIN) is greater than C X(MAX) , the system does not meet
the VID OTF specifications and may require less inductance.
In addition, the switching frequency may have to be increased
to maintain the output ripple.
For example, if two pieces of 22 m F, 0805 ? size MLC
capacitors (C Z = 44 m F) are used during a VID voltage
change, the V CC change is 220 mV in 22 m s with a setting
error of 10 mV. If k = 3.1, solving for the bulk capacitance
yields:
560 nH 8A
C X(MIN) w 10 mV * 44 m F
8A
+ 246 m F
560 nH 220 mV
3.1 2 (5.1 m W ) 2 1.174 V
low ? side switch. The main selection parameters for the
power MOSFETs are V GS(TH) , Q G , C ISS , C RSS , and
R DS(ON) . Because the voltage of the gate driver is 5.0 V,
logic ? level threshold MOSFETs must be used.
The maximum output current, I O , determines the R DS(ON)
requirement for the low ? side (synchronous) MOSFETs.
With conduction losses being dominant, the following
expression shows the total power that is dissipated in each
synchronous MOSFET in terms of the ripple current per
phase (I R ) and the average total output current (I O ):
2 2
h SF 12 h SF
(eq. 16)
where:
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
I R is the inductor peak ? to ? peak ripple current and is
approximately:
(1 * D) V OUT
L f sw
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the
required R DS(ON) for the MOSFET. For an 8 ? lead SOIC or
8 ? lead SOIC ? compatible MOSFET, the
1 )
22 m s
1.174 V
220 mV
3.1
560 nH
5.1 m W
* 1 * 44 m F
junction ? to ? ambient (PCB) thermal impedance is 50 ° C/W.
In the worst case, the PCB temperature is 70 ° C to 80 ° C
during heavy load operation of the notebook, and a safe limit
+ 992 m F
Using two 220 m F Panasonic SP capacitors with a typical
ESR of 7 m W each yields C X = 440 m F and R X = 3.5 m W .
for P SF is about 0.8 W to 1.0 W at 120 ° C junction
temperature. Therefore, for this example (15 A maximum),
the R DS(SF) per MOSFET is less than 18.8 m W for the
http://onsemi.com
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| NCP5380MNR2G | 功能描述:DC/DC 开关控制器 IMVP6.5 BUCK CTRL RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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| NCP5381AMNR2G | 功能描述:DC/DC 开关控制器 2/3/4 PHASE CNTRLR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| NCP5381MNR2G | 功能描述:DC/DC 开关控制器 ANA 2/3/4 PHSE BUCK CNTLR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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