参数资料
型号: NCP5380AMNR2G
厂商: ON Semiconductor
文件页数: 24/28页
文件大小: 0K
描述: IC CTLR SYNC BUCK SGL 32QFN
标准包装: 5,000
应用: 控制器,Intel VR11
输入电压: 5V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 带卷 (TR)
NCP5380, NCP5380A
sets the gain of the output current monitor. A 0.1 m F is placed
in parallel with R MON to filter the inductor current ripple and
high frequency load transients. Since the IMON pin is
connected directly to the CPU, it is clamped to prevent it
from going above 1.15 V.
VOLTAGE ERROR
AMPLIFIER
+
?
COMP FB
REFERENCE
VOLTAGE
NCP5380
R LIM
R MON +
R O
I FS
The IMON pin current is equal to the R LIM times a fixed gain
of 10. R MON can be found using the following equation:
1.15 V
(eq. 23)
10
Where:
R A
C B
C A
C FB
R FB
OUTPUT
VOLTAGE
R MON is the current monitor resistor. R MON is connected
from IMON pin to FBRTN.
Figure 25. Voltage Error Amplifier
R LIM is the current limit resistor.
R O is the output load line resistance.
I FS is the output current when the voltage on IMON is at full
scale.
Feedback Loop Compensation Design
Optimized compensation of the NCP5380/A allows the
GAIN
? 20dB/DEC
? 20dB/DEC
best possible response of the regulator ’s output to a load
change. The basis for determining the optimum
compensation is to make the regulator and output
0dB
f P1
f Z2 f Z1
f P2
FREQUENCY
f Z1 +
2 p
C A
R A
f Z2 +
2 p
C FB
R FB
f P1 +
f P2 +
2 p
R A
C B
C A
decoupling appear as an output impedance that is entirely
resistive over the widest possible frequency range, including
dc, and that is equal to the droop resistance (R O ). With the
resistive output impedance, the output voltage droops in
proportion with the load current at any load current slew
rate, ensuring the optimal position and allowing the
minimization of the output decoupling.
With the multimode feedback structure of the
NCP5380/A, it is necessary to set the feedback
compensation so that the converter ’s output impedance
works in parallel with the output decoupling. In addition, it
is necessary to compensate for the several poles and zeros
created by the output inductor and decoupling capacitors
(output filter).
A Type III compensator on the voltage feedback is
adequate for proper compensation of the output filter.
Figure 25 shows the Type III amplifier used in the
NCP5380/A. Figure 26 shows the locations of the two poles
and two zeros created by this amplifier.
Figure 26. Poles and Zeros of Voltage Error
The following equations give the locations of the poles
and zeros shown in Figure 26:
1
(eq. 24)
1
(eq. 25)
1
(eq. 26)
2 p C A ) C B R FB
1
(eq. 27)
The expressions that follow compute the time constants for
the poles and zeros in the system and are intended to yield
an optimal starting point for the design; some adjustments
may be necessary to account for PCB and component
parasitic effects (see the Tuning Procedure for NCP5380/A
section):
R E + R O ) A D
R DS )
R L V RT
V VID
(eq. 28)
)
2
L
(1 * (n
C X R O
D))
V VID
V RT
T A + C X
R O * R )
L X
R O
R O * R
R X
(eq. 29)
http://onsemi.com
24
T B + R X ) R * R O
C X
(eq. 30)
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