参数资料
| 型号： | NCP5425DB |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20TSSOP |
| 产品变化通告： | Product Obsolescence 14/Apr/2010 |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 938kHz |
| 占空比： | 100% |
| 电源电压： | 4.75 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
NCP5425
Output Inductor Selection
The number of output capacitors is determined by:
The inductor should be selected based on the criteria of
inductance, current capability, and DC resistance.
Increasing the inductor value will decrease output voltage
Number of capacitors +
ESRCAP
ESRMAX
IL(PEAK) + IOUT )
IL(VALLEY) + IOUT )
LMIN +
ripple, but degrade transient response. There are many
factors to consider in selecting inductors including cost,
efficiency, EMI and ease of manufacture. The inductor must
be able to handle the peak current at the switching frequency
without saturating, and the copper resistance in the winding
should be kept as low as possible to minimize resistive
power loss.
There are a variety of materials and types of magnetic
cores that could be used, such as ferrites, molypermalloy
cores (MPP), and amorphous and powdered iron cores.
Powdered iron cores are particularly suitable due to high
saturation flux density and low loss at high frequencies, a
distributed gap, and they produce very low EMI. The
minimum value of inductance to prevent inductor
saturation, or exceeding the rated FET current, can be
calculated as follows:
(VIN(MIN) * VOUT)VOUT
fSW VIN(MIN) ISW(MAX)
where:
L MIN = minimum inductance value;
V IN (MIN) = minimum design input voltage;
V OUT = output voltage;
f SW = switching frequency;
I SW (MAX) = maximum design switch current.
The inductor ripple current can then be determined by:
where:
ESR CAP = maximum ESR per capacitor
(specified in manufacturer ’s data sheet).
The designer must also verify that the inductor value
yields reasonable inductor peak and valley currents (the
inductor current is a triangular waveform):
D IL D IL
2 2
where:
I L(PEAK) = inductor peak current;
I L(VALLEY) = inductor valley current;
I OUT = load current;
D I L = inductor ripple current.
Output Capacitor Selection
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are ESR
(Equivalent Series Resistance) and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required. To determine the number of
output capacitors the maximum voltage transient allowed
during load transitions has to be specified. The output
capacitors must hold the output voltage within these limits
D IL +
VOUT
L
where:
D IL = inductor ripple current;
(1 * D)
fSW
since the inductor current can not change at the required slew
rate. The output capacitors must therefore have a very low
ESL and ESR.
The voltage change during the load current transient is
given by:
ESL ) ESR ) tTR
V OUT = output voltage;
L = inductor value;
D = duty cycle;
D VOUT + D IOUT
D t COUT
f SW = switching frequency.
After inductor selection, the designer can verify if the
number of output capacitors will provide an acceptable
output voltage ripple (1.0% of output voltage is common).
The formula below is used;
where:
D I OUT /D D = load current slew rate;
D I OUT = load transient;
D t = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
D IL +
D VOUT
ESRMAX
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
where:
ESR MAX = maximum allowable ESR;
D V OUT = 1.0% ? VOUT = maximum allowable output
voltage ripple (budgeted by the designer);
D I L = inductor ripple current;
V OUT = output voltage.
Rearranging, we have:
t TR = output voltage transient response time;
C OUT = output capacitance.
The designer must independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike,
depending on the load current transition) results from the
ESRMAX +
D VOUT
D IL
total output capacitor ESR.
http://onsemi.com
14
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