参数资料
| 型号： | NCP5425DB |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20TSSOP |
| 产品变化通告： | Product Obsolescence 14/Apr/2010 |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 938kHz |
| 占空比： | 100% |
| 电源电压： | 4.75 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
NCP5425
where:
I RMS(H) = maximum switching MOSFET RMS current;
I L(PEAK) = inductor peak current;
Synchronous (Lower) FET Selection
The switch conduction losses for the lower FET are
calculated as follows:
I L(VALLEY) = inductor valley current;
PRMS(L) + IRMS2
RDS(ON)
D = duty cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated by:
where:
+ IOUT
(1 * D) 2
RDS(ON)
where:
PRMS(H) + IRMS(H)2
RDS(ON)
P RMS(L) = lower MOSFET conduction losses;
I OUT = load current;
D = Duty Cycle;
+
P RMS(H) = switching MOSFET conduction losses;
I RMS(H) = maximum switching MOSFET RMS current;
R DS(ON) = FET drain?to?source on?resistance.
Upper MOSFET switching losses occur during MOSFET
switch?on and switch?off, and can be calculated by:
PSWH + PSWH(ON) ) PSWH(OFF)
VIN IOUT (tRISE ) tFALL)
6T
where:
P SWH(ON) = upper MOSFET switch?on losses;
P SWH(OFF) = upper MOSFET switch?off losses;
V IN = input voltage;
I OUT = load current;
T RISE =MOSFET rise time (from FET manufacturer ’s
switching characteristics performance curve);
TFALL = MOSFET fall time (from FET manufacturer ’s
switching characteristics performance curve);
T = 1/f SW = period.
The total power dissipation in the switching MOSFET can
then be calculated as:
PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)
where:
P HFET(TOTAL) = total switching (upper) MOSFET losses;
P RMS(H) = upper MOSFET switch conduction Losses;
P SWH(ON) = upper MOSFET switch?on losses;
P SWH(OFF) = upper MOSFET switch?off losses.
Once the total power dissipation in the switching FET is
R DS(ON) = lower FET drain?to?source on?resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non?overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
PSWL + VSD ILOAD non?overlap time fSW
where:
P SWL = lower FET switching losses;
V SD = lower FET source?to?drain voltage;
I LOAD = load current;
Non?overlap time = GATE(L)?to?GATE(H) or
GATE(H)?to?GATE(L) delay
(from NCP5425 data sheet
Electrical Characteristics section);
f SW = switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PLFET(TOTAL) + PRMS(L) ) PSWL
where:
P LFET(TOTAL) = Synchronous (lower) FET total losses;
P RMS(L) = Switch Conduction Losses;
P SWL = Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
known, the maximum FET switch junction temperature can
be calculated:
TJ + TA ) [PHFET(TOTAL) R q JA]
TJ + TA ) [PLFET(TOTAL)
where:
T J = MOSFET junction temperature;
R q JA]
where:
T J = FET junction temperature;
T A = ambient temperature;
P HFET(TOTAL) = total switching (upper) FET losses;
T A = ambient temperature;
P LFET(TOTAL) = total synchronous (lower) FET losses;
R q JA = lower FET junction?to?ambient thermal
resistance.
R q JA = upper FET junction?to?ambient thermal
resistance.
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