参数资料
| 型号： | NCP5425DB |
| 厂商： | ON Semiconductor |
| 文件页数： | 20/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20TSSOP |
| 产品变化通告： | Product Obsolescence 14/Apr/2010 |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 938kHz |
| 占空比： | 100% |
| 电源电压： | 4.75 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
NCP5425
Grounding the Mode pin enables an internal clamp to limit
the Comp 2 voltage excursions during overcurrent faults.
Without this clamp, the output voltage (Vout1 and Vout2)
can overshoot the regulated output voltages when the fault
is removed. For a single output two?phase application the
Mode pin must be floating, which disables the clamp and
permits a larger current?sharing reference voltage range.
The Comp1 pin is always clamped, because it is regulated to
a fixed internal voltage (0.8 V).
Q1
Vout1
L1
Vin
The simplest way to provide a Controller 2 reference is by
using the Controller 1 feedback voltage. This will provide a
0.8 V reference for regulation, and also causes the
Controller 2 output to track the Controller 1 output during
transients. With a voltage reference established and the
Mode pin floating, Controller 2 can function as an
independent Buck regulator.
Q3
Vout2
L2
Q2
C1
R1
R3
C2
Q4
Master
?
+
Vfb1
Vref1
R2
R4
Vfb2
Vref2
?
+
Slave
Error Amp
Internal
0.8 V Ref.
Figure 15. Dual Output Configuration
Error Amp
Adding External Slope Compensation
Today’s voltage regulators are expected to meet very
stringent load transient requirements. One of the key factors
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that very little
voltage ramp exists at the control IC feedback pin (VFB),
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the
t = RC constant determined by C1 and the parallel
combination of R1, R2 neglecting the low driver
output impedance.
COMP
NCP5425
internal slope compensation is insufficient, the performance
R2
C1
R1
of the NCP5425?based regulator can be improved through
the addition of a fixed amount of external slope
compensation at the output of the PWM Error Amplifier (the
COMP pin) during the regulator off?time. Referring to
Figure 8, the amount of voltage ramp at the COMP pin is
GATE(L)
To Synchronous
FET
dependent on the gate voltage of the lower (synchronous)
FET and the value of resistor divider formed by R1and R2.
Figure 16. RC Filter Provides the Proper Voltage
Ramp at the Beginning of each On?Time Cycle
(1?e ?1 )
VSLOPECOMP + VGATE(L)
R2
R1 ) R2
t
The artificial voltage ramp created by the slope
where:
V SLOPECOMP = amount of slope added;
V GATE(L) = lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t ON or t OFF (switch off?time);
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off?time cycle duration (time during which the lower
MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.
http://onsemi.com
20
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