参数资料
| 型号： | NCP5425DB |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20TSSOP |
| 产品变化通告： | Product Obsolescence 14/Apr/2010 |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 938kHz |
| 占空比： | 100% |
| 电源电压： | 4.75 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
NCP5425
output voltage exceeds the COMP pin voltage, minus the
0.3 V PWM comparator offset threshold and the artificial
ramp, the PWM comparator terminates the initial pulse.
Transient Response
The 200 ns reaction time of the control loop provides fast
transient response to any variations in input voltage or
output current. Pulse?by?pulse adjustment of duty cycle is
4.2 V
V IN
V COMP
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, a combination of
0.3 V
V FB
GATE(H)1
several high frequency and bulk output capacitors are
typically used.
Out?of?Phase Synchronization
The turn?on of the second channel is delayed by half the
switching cycle. This delay is supervised by the oscillator,
UVLO
STARTUP
GATE(H)2
t s NORMAL OPERATION
which supplies a clock signal to the second channel that is
180 ° out of phase with the clock signal of the first channel.
Advantages of out?of?phase synchronization are many.
Figure 4. Idealized Startup Waveforms
Normal Operation
During normal operation, the duty cycle remains
approximately constant as the V 2 control loop maintains
regulated output voltage under steady state conditions.
Variations in supply line or output load conditions will result
in changes in duty cycle to maintain regulation.
Gate Charge Effect on Switching Times
When using the on board gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading,
according to the following graphs.
90
80
Since the input current pulses are interleaved with one
another, the overlap time is reduced. Overlap reduction
reduces the input filter requirement, allowing the use of
smaller components. In addition, since peak current occurs
during a shorter time period, emitted EMI is also reduced,
potentially reducing shielding requirements. Interleaving
the phases in a two phase application reduces ripple voltage
and allows supplies with tighter tolerances to be built.
Overvoltage Protection
Overvoltage Protection (OVP) is provided as a
consequence of the normal operation of the V 2 control
method, and requires no additional external components to
implement. The control loop responds to an overvoltage
condition within 200 ns, turning off the upper MOSFET and
disconnecting the regulator from its input voltage. This
results in a crowbar action to clamp the output voltage,
preventing damage to the load. The regulator remains in this
state until the overvoltage condition clears.
70
60
50
40
30
20
10
0
Average Rise Time
Average Fall Time
Low Noise Disable Mode
A PWM converter operating at a constant frequency
concentrates its noise output over a small frequency band. In
noise?sensitive applications, this frequency can be chosen
to prevent interference with other system functions. Some
applications may have even more stringent requirements,
where absolutely no noise may be emitted for a short period
of time.
The user may disable the clock during noise sensitive
periods to temporarily inhibit switching noise by
0
0
2
3
4
5
6
7
8
disconnecting or pulling the R OSC pin to 3.3 V. This disables
LOAD (nF)
Figure 5. Average Rise and Fall Times
both gate drivers, leaving the switch node floating, and
discharges the internal ramp.
The control circuitry remains enabled while the clock and
drivers are disabled, so the COMP pins will charge up to a
higher voltage. The COMP pins are clamped to prevent
excessive overshoot when switching is resumed.
http://onsemi.com
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