参数资料
型号: NCV7361ADR2G
厂商: ON Semiconductor
文件页数: 12/27页
文件大小: 0K
描述: IC REG LDO 5V 50MA 8-SOIC
产品变化通告: Product Discontinuation 27/Jan/2012
标准包装: 2,500
稳压器拓扑结构: 正,固定式
输出电压: 5V
输入电压: 5.25 V ~ 18 V
稳压器数量: 1
电流 - 输出: 50mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
NCV7361A
V SUP
V SUVR_OFF
V SUVR_ON
Mode
Control
Input
UVR
POR
EN = H/L
POR
UVR
(internal*)
Normal Mode
Sleep Mode
Normal Mode
V OUT
*reference Figure 1 Block Diagram
Figure 16. Operating of Power On and Undervoltage RESET
Switching into sleep mode can be done independently
from the current transceiver state. That means if the
transmitter is in dominant state this state will be cancelled
and it will be switched to recessive state.
POR ? state
This is the power ? on ? reset state of the NCV7361A,
while V SUP < V SUVR_OFF . If the prior state was sleep mode,
the NCV7361A switches via the Ini ? state to normal mode.
Ini ? state
This is an intermediate state, which will pass through
after switch ? on of V SUP or V OUT . The NCV7361A remains
in this state if V OUT is below V RES (Reset Output = L) and
V SUP > V SUVR_ON .
Thermal Shutdown
If the junction temperature T J is higher than T JSHD
(>155 ° C), the NCV7361A will be switched into the
thermal shutdown mode. The behavior within this mode is
comparable with the sleep mode except for LIN transceiver
operating. The transceiver is completely disabled, no
wake ? up functionality is available.
If T J falls below the thermal recovery temperature T JREC
(typical 140 ° C) the NCV7361A will be recover to the
previous state (normal or sleep).
Initialization
Initialization is started if the power supply is switched on
as well as every rising edge on of the NCV7361A via the
EN pin.
V SUP ? Power On
If V SUP is switched on the NCV7361A starts to normal
mode via the POR ? and Ini ? state. A combination of
dynamic POR and undervoltage reset circuitry generates a
POR signal, which switches the NCV7361A into normal
mode. This power on behavior is independent from the
status of the EN pin.
Power ? on ? Reset and undervoltage reset operates
independent from each other, which secures the
independence from the rise time of V SUP . During fast V SUP
edges the Power ? on ? Reset will be active. If the increasing
of V SUP is very slow (> 1 ms/V) the undervoltage reset unit
initializes the voltage regulator if V SUP > V SUVR_OFF
(typical 3.5 V).
The effects of both POR circuits at different V SUP slopes
as shown in Figure 16.
After POR the voltage regulator starts and V OUT will be
output. If V OUT > V MRes the bus interface will be activated.
If the V OUT voltage level is higher than V RES , the reset time
t Res = 100 ms is started. After t Res the RESET output
switches from low to high (Figure 16).
Start of Linear Regulator via Wake ? Up
The initialization is only being done for the V OUT
circuitry parts. This procedure begins with leaving the
master reset state (V OUT > V MRes ) and runs in the same
manner as the V SUP ? Power ? On.
Wake ? Up
If the regulator is put into sleep mode it can be
“waked ? up” with the BUS interface. Every pulse on the
BUS (high pulse or low pulse) with a pulse width of
minimum 60 m s switches on the regulator.
After the BUS has “waked ? up” the regulator, it can only
be switched off with a high level followed by a low level
on the EN pin.
V SUP Undervoltage Reset
The undervoltage detection unit inhibit an undefined
behavior of the NCV7361A under low voltage condition.
If V SUP drops below V SUVR_ON (typical 3 V) the
undervoltage detection becomes active and the IC will be
switched to POR state. The following increasing of V SUP
above V SUVR_OFF (typical 3.5 V) cancels this POR state
and the voltage regulator starts with the initialization
sequence.
V SUP Undervoltage in Normal Mode
Supply Voltages below V SUVR_OFF do not influence the
voltage regulator. The output voltage V OUT follows V SUP .
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