参数资料
| 型号： | NCV7361ADR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/27页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V 50MA 8-SOIC |
| 产品变化通告： | Product Discontinuation 27/Jan/2012 |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 5.25 V ~ 18 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 50mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
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NCV7361A
V SUP
60%
V thr_max
BUS
50%
V thr_hys
V thr_cnt
40%
V thr_min
t < t deb_BUS
t < t deb_BUS
RxD
Figure 18. Receive Mode Impulse Diagram
The receive threshold values V thr_max and V thr_min are
symmetrical to 0.5*V SUP with a hysteresis of 0.135*V SUP .
The LIN specific receive threshold is between 0.4*V SUP
and 0.6 * V SUP .
Data Rate
The NCV7361A is a constant slew rate transceiver. The
bus driver works with a fixed slew rate range of 1.0 V/ m s
v D V/ D T v 2.5 V/ m s. This principle provides good
symmetry of the slope times between recessive to dominant
and dominant to recessive slopes within the LIN bus load
range (C BUS , R term ).
The NCV7361A guarantees data rates up to 20 kb within
the complete bus load range under worst case conditions.
The constant slew rate principle holds appropriate voltage
levels and can operate within the LIN Protocol
Specification for RC oscillator systems with a matching
tolerance up to " 2% between 2 nodes.
TxD Input
The 5.0 V input TxD directly controls the BUS level:
TxD = low → BUS = low (dominant level)
TxD = high → BUS = high (recessive level)
The TxD pin has an internal pullup resistor connected to
V OUT . This guarantees that an open TxD pin generates a
recessive BUS level.
MCU
V CC
R PU_TxD
V OUT
Typ.
15 k
NCV7361A
RC Filter
I PU_TxD
(10 ns)
TxD
Figure 19. TxD Input Circuitry
http://onsemi.com
14
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