参数资料
| 型号： | NCV7361ADR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/27页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V 50MA 8-SOIC |
| 产品变化通告： | Product Discontinuation 27/Jan/2012 |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 5.25 V ~ 18 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 50mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
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NCV7361A
V SUP Undervoltage in Sleep Mode
No exit from the sleep mode will take place if the V SUP
voltage drops down to V SUVR_ON (typical 3.0 V). The
undervoltage reset becomes active (POR ? state). As a result
of this operating, the sleep mode is left to the normal mode.
If V SUP rises again above V SUVR_OFF (typical 3.5 V), the
IC initializes the voltage regulator and continues to work
with the normal mode.
The undervoltage reset unit secures stable operating in
the undervoltage range of V SUP down to GND level. The
dynamic Power ? On ? Reset secures a defined internal state
independent from the duration of the V SUP drop, which
secures a stable restart.
Overtemperature Shutdown
If the junction temperature is 155 ° C < T J < 170 ° C the
overtemperature recognition will be activated and the
regulator voltage will be switched off. The V OUT voltage
drops down, the reset state is entered and the
bus ? transceiver is switched off (recessive state).
After T J falls below 140 ° C the NCV7361A will be
initialized again (Figure 17) independently from the
voltage levels on EN and BUS. Within the thermal
shutdown mode the transceiver can not be switched to the
normal mode neither with local nor with remote wake ? up.
The operation of the NCV7361A is possible between
T Amax (125 ° C) and the switch ? off temperature, but small
parameter differences can appear.
After overtemperature switch ? off the IC behaves as
described in Figure 17.
V SUP
LIN BUS Transceiver
The NCV7361A is a bidirectional bus interface device
for data transfer between the LIN bus and the LIN protocol
controller.
The transceiver consists of a pnp ? driver (1.2 V @
40 mA) with slew rate control, wave shaping and current
limit, and a high voltage receiver/comparator followed by
a filter circuit.
Transmit Mode
During transmission the data at the TxD pin will be
transferred to the BUS driver for generating a BUS signal.
To minimize the electromagnetic emission of the bus line,
the BUS driver has integrated slew rate control and wave
shaping circuitry.
Transmitting will be interrupted in the following cases:
? Sleep Mode
? Thermal Shutdown Active
? Master Reset (V OUT < 3.15 V)
The recessive BUS level is generated from the integrated
30 k pullup resistor in series with a diode This diode
prevents reverse current on V BUS when V BUS > V SUP .
No additional termination resistor is necessary to use the
NCV7361A in LIN slave nodes. If this IC is used for LIN
master nodes, it is necessary to terminate the bus pin with
an external 1.0 k W resistor in series with a diode to V BAT .
Receive Mode
The data signal from the BUS pin will be transferred
continuously to the pin RxD. Short spikes on the bus are
suppressed by the internal filter circuit ( t = 2.8 m s).
V OUT
T>T J
T<T J
t<t rr
t<t rr
V RES
t Res
t rr
t Res
t Res
t Res
RESET
Initialization
Thermal
shutdown
Spike V SUP
Low voltage
V SUP
Spike V CC
Current limitation
active
Figure 17. RESET Behavior
http://onsemi.com
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