参数资料
型号: NCV7703BD2R2G
厂商: ON Semiconductor
文件页数: 12/16页
文件大小: 0K
描述: IC DVR HALF BRIDGE TRPL 14SOIC
标准包装: 2,500
类型: 半桥
输入类型: SPI
输出数: 3
导通状态电阻: 800 毫欧
电流 - 输出 / 通道: 500mA
电流 - 峰值输出: 1A
电源电压: 5.5 V ~ 40 V
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOICN
包装: 带卷 (TR)
NCV7703B
Table 1. SPI BIT DESCRIPTION
Input Data
Output Data
Bit Number
15
14
Bit Description
Over Voltage Lock Out
Control (OVLO)
Not Used
Bit Status
0 = Disable
1 = Enable
Bit Number
15
14
Bit Description
Power Supply Fail Signal
(PSF for OVLO or UVLO)
Under Load Detect Signal (ULD)
Bit Status
0 = No Fault
1 = Fault
0 = No Fault
1 = Fault
13
Over Current Detection Shut
0 = Disable
13
Over Load Detect Signal (OLD)
0 = No Fault
Down Control (OCD)
1 = Enable
1 = Fault
12
11
10
9
8
7
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
12
11
10
9
8
7
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
6
OUTH3
0 = Off
6
OUTH3
0 = Off
1 = On
1 = On
5
OUTL3
0 = Off
5
OUTL3
0 = Off
1 = On
1 = On
4
OUTH2
0 = Off
4
OUTH2
0 = Off
1 = On
1 = On
3
OUTL2
0 = Off
3
OUTL2
0 = Off
1 = On
1 = On
2
OUTH1
0 = Off
2
OUTH1
0 = Off
1 = On
1 = On
1
OUTL1
0 = Off
1
OUTL1
0 = Off
1 = On
1 = On
0
Status Register Reset (SRR)
0 = No Reset
0
Thermal Warning (TW)
0 = Not in TW
1 = Reset
DETAILED OPERATING DESCRIPTION
1 = In TW
General
The NCV7703B Triple Half Bridge Driver provides drive
capability for 3 Half?Bridge configurations. Each output
drive is characterized for a 500 mA load and has a typical
1.4 A surge capability. Strict adherence to integrated circuit
die temperature is necessary, with a maximum die
temperature of 150 ° C. This may limit the number of drivers
enabled at one time. Output drive control and fault reporting
are handled via the SPI (Serial Peripheral Interface) port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. A pull
down is provided on the EN, SI and SCLK inputs to ensure
they default to a low state in the event of a severed input
Power Up/Down Control
A feature incorporated in the IC is an under voltage
lockout circuit that prevents the output drivers from turning
on unintentionally. V CC and V S are monitored for
undervoltage conditions supporting a smooth turn?on
transition. All drivers are initialized in the off (high
impedance) condition, and will remain off during a V CC or
V S undervoltage condition. This allows power up
sequencing of V CC , and V S up to the user. Once V CC is out
of UVLO, SPI communication can begin regardless of the
voltage on V S . However, drivers will remain off if V S is in
an undervoltage condition. Hysteresis in the UVLO circuits
results in glitch free operation during power up/down.
signal. A pull?up is provided on the CSB input disabling SPI
communication in the event of an open CSB input.
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