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参数资料
| 型号： | NT1GT72U8PA0BE-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 14/20页 |
| 文件大小： | 396K |
| 代理商： | NT1GT72U8PA0BE-3C |
NT512T72U89A5BD / NT512T72U89A2BN / NT512T72U89A0BE
NT1GT72U8PA3BD / NT1GT72U8PA2BN / NT1GT72U8PA0BE
Preliminary
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 0.6
3
02/27/2006
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DIMM Connector Pin Description
Pin Name
Pin Description
Note
SCK
System Clock Input, positive line
1
System Clock Input, negative line
1
PN0-PN13
Primary Northbound Data, positive lines
-
Primary Northbound Data, negative lines
PS0-PS9
Primary Southbound Data, positive lines
-
Primary Southbound Data, negative lines
SN0-SN13
Secondary Northbound Data, positive lines
-
Secondary Northbound Data, negative lines
SS0-SS9
Secondary Southbound Data, positive lines
-
Secondary Southbound Data, negative lines
SCL
Serial Presence Detect (SPD) Clock Input
SDA
SPD Data Input / Output
SA0-SA2
SPD Address Inputs, also used to select the DIMM number in the AMB
VID0-VID1
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID0 is VDD value: OPEN=1.8V, GND=1.5V; VID1 is VCC value: OPEN=1.5V, GND=1.2V
AMB reset signal
RFU
Reserved for Future Use
2
VCC
AMB Core Power and AMB Channel Interface Power (1.5V)
VDD
DRAM Power and AMB DRAM I/O Power (1.8V)
VTT
DRAM Address/Command/Clock Termination Power (VDD/2)
VDDSPD
SPD Power (3.3V)
VSS
Ground
DNU/M_TEST
It provides an external connection on R/Cs A-D for testing the margin of Vref which is
produced by a voltage divider on the module. It is not intended to be used in normal
system operation and must not be connected (DNU) in a system. This test pin may have
other features on future card designs and if it does, will be included in this specification at
that time.
1
Note:
1.
System Clock Signals SCK and SCK switch at one half the DRAM CK/
frequency
2.
Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
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