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参数资料
| 型号： | NT1GT72U8PA0BE-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 20/20页 |
| 文件大小： | 396K |
| 代理商： | NT1GT72U8PA0BE-3C |
NT512T72U89A5BD / NT512T72U89A2BN / NT512T72U89A0BE
NT1GT72U8PA3BD / NT1GT72U8PA2BN / NT1GT72U8PA0BE
Preliminary
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 0.6
9
02/27/2006
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 1 of 2
512MB, 1 RANK Fully Buffered DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
DDR2-533 DDR2-667 DDR2-533 DDR2-667
Byte
Description
-4B
-3C
-4B
-3C
Note
0
Number of Serial PD Bytes Written / SPD Device Size / CRC
Coverage
Size = 256;
CRC = 116;
Used byte = 176
92
1
SPD Revision
Rev 1.0
10
2
Key Byte / DRAM Device Type
DDR2 FB-DIMM
09
3
Voltage Levels of this Assembly
DRAM = 1.8V;
Channel = 1.5V
12
4
SDRAM Addressing
Row = 14;
Col = 10;
Bank = 4
44
5
Module Physical Attributes
30~35mm height
8~9mm thick
24
6
Modules Type / Thickness
FB-DIMM 133.35mm
07
7
Module Organization
1 rank
x8 device width
09
8
Fine Timebase Dividend and Divisor
2.5ps
5ps
52
51
9
Medium Timebase Dividend
1(0.25ns)
01
10
Medium Timebase Divisor
4(0.25ns)
04
11
SDRAM Minimum Cycle Time (tCKmin)
3.75ns
(266MHz)
3ns
(333MHz)
0F
0C
12
SDRAM Maximum Cycle Time (tCKmax)
8ns(125MHz)
20
13
SDRAM
Latencies Supported
2,4
4,5
24
45
14
SDRAM Minimum CAS Latency Time (tCAS)
15ns
3C
15
SDRAM Write Recovery Times Supported
1,4
1,5
14
15
16
SDRAM Write Recovery Time (tWR)
15ns
3C
17
SDRAM Write Latencies Supported
2,3
1,4
23
14
18
SDRAM Additive Latencies Supported
4,0
40
19
SDRAM Minimum
to
Delay (tRCD)
15ns
3C
20
SDRAM Minimum Row Active to Row Active Delay (tRRD)
7.5ns
1E
21
SDRAM Minimum Row Precharge Time (tRP)
15ns
3C
22
SDRAM Upper Nibbles for tRAS and tRC
0
00
23
SDRAM Minimum Active to Precharge Time (tRAS)
45ns
B4
24
SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC)
60ns
55ns
F0
DC
25~26 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command
Period (tRFC)
105ns
A401
27
SDRAM Internal Write to Read Command Delay (tWTR)
7.5ns
1E
28
SDRAM Internal Read to Precharge Command Delay (tRTP)
7.5ns
1E
29
SDRAM Burst Lengths Supported
BL8, BL4
03
30
SDRAM Terminations Supported
50/75/150
75/150
07
03
31
SDRAM Drivers Supported
Supported
01
32
SDRAM Average Refresh Interval (tREFI)/Double Refresh mode
bit/High Temperature self-refresh rate support indication
7.8us, 2x hot refresh
(temp>85C),
hot self-refresh
C2
33
Tcasemax
0°C
50
34
Thermal resistance of SDRAM device package from top (case0 to
ambient (Psi T-A SDRAM)
122C/W
7A
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