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参数资料
| 型号： | NT1GT72U8PA0BE-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 9/20页 |
| 文件大小： | 396K |
| 代理商： | NT1GT72U8PA0BE-3C |
NT512T72U89A5BD / NT512T72U89A2BN / NT512T72U89A0BE
NT1GT72U8PA3BD / NT1GT72U8PA2BN / NT1GT72U8PA0BE
Preliminary
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 0.6
17
02/27/2006
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
-4B
-3C
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit Notes
tAC
DQ output access time from CK/
-0.5
+0.5 -0.45 +0.45
ns
tDQSCK
DQS output access time from CK/
-0.45 +0.45
-0.4
+0.4
ns
tCH
CK high-level width
0.45
0.55
0.45
0.55
tCK
tCL
CK low-level width
0.45
0.55
0.45
0.55
tCK
tHP
Minimum half clk period for any given cycle;
defined by clk high (tCH) or clk low (tCL) time
tCH
or
tCL
-
tCH
or
tCL
-
tCK
tCK
Clock Cycle Time
3.75
8
3
8
ns
tDH
DQ and DM input hold time
225
-
175
-
ps
tDS
DQ and DM input setup time
100
-
100
-
ps
tIPW
Input pulse width
0.6
-
0.6
-
tCK
tDIPW
DQ and DM input pulse width (each input)
0.35
-
0.35
-
tCK
tHZ
Data-out high-impedance time from CK/
-
tAC max
-
tAC max
ns
tLZ(DQ)
Data-out low-impedance time from CK/
2tAC
min
tAC max 2tAC
min
tAC max
ns
tLZ(DQS) DQS/
low-impedance time from CK/
tAC min tAC max tAC min tAC max
ns
tDQSQ
DQS-DQ skew (DQS & associated DQ signals)
-
0.30
-
0.24
ns
tQHS
Data hold Skew Factor
-
0.4
-
0.34
ns
tQH
Data output hold time from DQS
tHP -
tQHS
-
tHP -
tQHS
-
ns
tDQSS
Write command to 1st DQS latching transition
-0.25
0.25
-0.25
0.25
tCK
tDQSL,(H)
DQS input low (high) pulse width
(write cycle)
0.35
-
0.35
-
tCK
tDSS
DQS falling edge to CK setup time
(write cycle)
0.2
-
0.2
-
tCK
tDSH
DQS falling edge hold time from CK
(write cycle)
0.2
-
0.2
-
tCK
tMRD
Mode register set command cycle time
2
-
2
-
tCK
tWPST
Write postamble
0.40
0.60
0.40
0.60
tCK
tWPRE
Write preamble
0.35
-
0.35
-
tCK
tIH
Address and control input hold time
375
-
275
-
ps
tIS
Address and control input setup time
0.25
-
0.2
-
ns
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tCK
tRPST
Read postamble
0.4
0.6
0.4
0.6
tCK
tDelay
Minimum time clocks remains ON after CKE
asynchronously drops Low
tIS +
tCK +
tIH
tIS +
tCK +
tIH
ns
tRFC
Refresh to active/Refresh command time
105
ns
Average Periodic Refresh Interval
(85C < TCASE < 95C)
3.9
=
s
tREFI
Average Periodic Refresh Interval
(0C < TCASE < 85C)
7.8
=
s
tRRD
Active bank A to Active bank B command
7.5
-
7.5
-
ns
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