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参数资料
| 型号： | NT1GT72U8PA0BE-3C |
| 厂商： | NANYA TECHNOLOGY CORP |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 8/20页 |
| 文件大小： | 396K |
| 代理商： | NT1GT72U8PA0BE-3C |
NT512T72U89A5BD / NT512T72U89A2BN / NT512T72U89A0BE
NT1GT72U8PA3BD / NT1GT72U8PA2BN / NT1GT72U8PA0BE
Preliminary
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 0.6
16
02/27/2006
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)
Symbol
Parameter/Condition
PC2-4200
(-4B)
Max.
PC2-5300
(-3C)
Max.
Unit
Notes
Idd_Idle_0
Idle Current, single or last DIMM. L0 state, idle (0BW). Primary channel
enabled; Secondary Channel disabled. CKE high. Command and address
line stable. DRAM clock active.
TBD
mA
Idd_Idle_1
Idle Current, first DIMM. L0 stage, idle (0BW). Primary and Secondary
channels enabled. CKE high. Command and address line stable. DRAM
clock active.
TBD
mA
Idd_Idle_2
Idle Current, DRAM power down. L0stage, idle (0BW). Primary and
Secondary channels enabled CKE low. Command and address lines
floated. DRAM clock active, ODT and CKE driven low.
TBD
mA
Idd_Active_1
Active Power. L0 state. 50% DRAM BW to downstream DIMM, 67% read,
33% write. Primary and Secondary channels enabled. DRAM clock active,
CKE high.
TBD
mA
Idd_Active_2
Active Power, data pass through. L0 state. 50% DRAM BW to
downstream DIMM, 67% read, 33% write. Primary and Secondary
channels enabled. CKE high. Command and address lines stable. DRAM
clock active.
TBD
mA
Idd_L0s
Channel Standby. Average power over 42 frames where the channel
enters and exits L0s. DRAMs Idle (0BW). CKE low. Command and
address lines floated. DRAM clock active, ODE and CKE driven low.
TBD
mA
Idd_Training
Primary and Secondary channels enabled. 100% toggle on all channel
lanes. DRAMs idle. 0BW. CKE high, Command and address line stable.
DRAM clock active.
TBD
mA
Note:
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