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参数资料
| 型号： | NT5DS64M4AW-75B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb Double Data Rate SDRAM |
| 中文描述： | 256MB双数据速率SDRAM |
| 文件页数： | 57/78页 |
| 文件大小： | 1534K |
| 代理商： | NT5DS64M4AW-75B |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
57
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Input Operating Conditions
(0 °C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Notes
V
IH(AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
V
REF
+ 0.31
V
1, 2
V
IL(AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
V
REF
0.31
V
1, 2
V
ID(AC)
Input Differential Voltage, CK and CK Inputs
0.62
V
DDQ
+ 0.6
V
1, 2, 3
V
IX(AC)
Input Crossing Point Voltage, CK and CK Inputs
0.5*V
DDQ
0.2
0.5*V
DDQ
+
0.2
V
1, 2, 4
1. Input slew rate = 1V/ns
.
2. Inputs are not recognized as valid until V
REF
stabilizes.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
I
DD
Specifications and Conditions
(0 °C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
DDR200
(8B)
t
CK
=10ns
DDR266A/B
(7K/75B)
t
CK
=7.5ns
Unit
Notes
I
DD0
Operating Current
: one bank; active / precharge; t
= t
(min); DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle
75
85
mA
1
I
DD1
Operating Current
: one bank; active / read / precharge; Burst = 2; t
= t
(min); CL = 2.5;
I
OUT
= 0mA; address and control inputs changing once per clock
cycle
90
110
mA
1
I
DD2P
Precharge Power-Down Standby Current
: all banks idle; power-down mode;
CKE
≤
V
IL
(max)
15
15
mA
1
I
DD2N
Idle Standby Current:
CS
≥
V
(min); all banks idle; CKE
≥
V
IH
(min);
address and control inputs changing once per clock cycle
30
35
mA
1
I
DD3P
Active Power-Down Standby Current
: one bank active; power-down mode;
CKE
≤
V
IL
(max)
15
15
mA
1
I
DD3N
Active Standby Current
: one bank; active / precharge; CS
≥
V
IH
(min);
CKE
≥
V
(min); t
= t
(max); DQ, DM, and DQS inputs changing twice per
clock cycle; address and control inputs changing once per clock cycle
50
60
mA
1
I
DD4R
Operating Current:
one bank; Burst = 2; reads; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS outputs changing
twice per clock cycle; CL = 2.5; I
OUT
= 0mA
130
165
mA
1
I
DD4W
Operating Current
: one bank; Burst = 2; writes; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS inputs changing twice
per clock cycle; CL = 2.5
115
150
mA
1
I
DD5
Auto-Refresh Current
: t
RC
= t
RFC
(min)
160
170
mA
1
I
DD6
Self-Refresh Current
: CKE
≤
0.2V
2
2
mA
1, 2
I
DD7
Operating curren
t: four bank; four bank interleaving with BL = 4, address
and
control inputs randomly changing; 50% of data changing at every transfer;
t
RC
= t
RC
(min); I
OUT
= 0mA.
TBD
TBD
mA
1
1. I
DD
specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
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|---|---|
| NT5DS64M4AW-7K | 256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-8B | 256Mb Double Data Rate SDRAM |
| NT5DS32M8AW | 256Mb DDR333/300 SDRAM |
| NT5DS32M8AW-6 | 256Mb DDR333/300 SDRAM |
| NT5DS32M8AW-66 | 256Mb DDR333/300 SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5DS64M4AW-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS64M4AW-8B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS64M4CS | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS64M4CS-5T | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS64M4CS-6K | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
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