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参数资料
| 型号： | NTE6508 |
| 厂商： | NTE Electronics, Inc. |
| 英文描述： | Integrated Circuit CMOS, 1K Static RAM (SRAM) |
| 中文描述： | 集成电路的CMOS，每1000静态RAM（SRAM） |
| 文件页数： | 2/4页 |
| 文件大小： | 37K |
| 代理商： | NTE6508 |
DC Electrical Characteristics:
V
CC
= 5V
±
10%, T
A
=
–
40
°
to +85
°
C unless otherwise specified)
Parameter
Symbol
Test Conditions
Standby Supply Current
I
CC(SB)
I
O
= 0, V
I
= V
CC
or GND, V
CC
= 5V
Operating Supply Current
I
CC(OP)
E = 1MHz, I
O
= 0, V
I
= V
CC
or GND,
V
CC
= 5.5V, Note 2
Data Retention Supply Current
I
CC(DR)
V
CC
= 2V, I
O
= 0, V
I
= V
CC
or GND,
E = V
CC
Data Retention Supply Voltage
V
CC(DR)
Input Leakage Current
I
I
V
I
= V
CC
or GND, V
CC
= 5.5V
Output Leakage Current
I
OZ
V
O
= V
CC
or GND, V
CC
= 5.5V
Input Voltage, LOW
V
IL
V
CC
= 4.5V
Input Voltage, HIGH
V
IH
V
CC
= 5.5V
Output Voltage, LOW
V
OL
I
O
= 3.2mA, V
CC
= 4.5V
Output Voltage, HIGH
V
OH
I
O
=
–
0.4mA, V
CC
= 4.5V
Min
–
–
Typ
–
–
Max
10
4
Unit
μ
A
mA
–
–
10
μ
A
2.0
–
1.0
–
1.0
–
0.3
V
CC
–
2
–
2.4
–
–
–
–
–
–
–
–
V
μ
A
μ
A
V
V
V
V
+1.0
+1.0
+0.8
V
CC
+0.3
0.4
–
Note 2. Typical derating 1.5mA/MHz increase in I
CC(OP)
.
Capacitance:
(T
A
= +25
°
C unless otherwise specified)
Parameter
Input Capacitance
Output Capacitance
Symbol
C
I
C
O
Test Conditions
Min
–
–
Typ
–
–
Max
6
10
Unit
pF
pF
f = 1MHz, All measurements are ref-
erenced to device GND
AC Electrical Characteristics:
V
CC
= 5V
±
10%, T
A
=
–
40
°
to +85
°
C unless otherwise specified)
Parameter
Symbol
Chip Enable Access Time
TELQV
Note 3, Note 5
Address Access Time
TAVQV
Note 3, Note 5, & Note 6
Chip Enable Output Enable Time
TELQX
Note 4, Note 5
Write Enable Output Disable Time
TWLQZ
Note 4, Note 5
Chip Enable Output Disable Time
TEHQZ
Note 4, Note 5
Chip Enable Pulse Negative Width
TELEH
Note 3, Note 5
Chip Enable Pulse Positive Width
TEHEL
Note 3, Note 5
Address Setup Time
TAVEL
Note 3, Note 5
Address Hold Time
TELAX
Note 3, Note 5
Data Setup Time
TDVWH
Note 3, Note 5
Data Hold Time
TWHDX
Note 3, Note 5
Chip Enable Write Pulse Setup Time
TWLEH
Note 3, Note 5
Chip Enable Write Pulse Hold Time
TELWH
Note 3, Note 5
Write Enable Pulse Width
TWLWH
Note 3, Note 5
Read or Write Cycle Time
TELEL
Note 3, Note 5
Test Conditions
Min
–
–
5
–
–
300
100
0
50
110
0
130
130
130
350
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
300
300
160
160
160
–
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 3. Input pulse levels: 0.8V to V
CC
–
2V; Input rise and fall times: 5ns (max); Input and output
timing reference level: 1.5V; Output load: 1 TTL gate equivalent, C
L
= 50pF (min)
–
for C
L
greater than 50pF, access time is derated by 0.15ns per pF.
Note 4. Tested at initial design and after major design changes.
Note 5. V
CC
= 4.5V and 5.5V.
Note 6. TAVQV = TELQV + TAVEL.
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