- 您现在的位置：买卖IC网 > PDF目录299577 > OR3T80-4B600 FPGA, 484 CLBS, 58000 GATES, PBGA600 PDF资料下载
参数资料
| 型号： | OR3T80-4B600 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, PBGA600 |
| 封装： | BGA-600 |
| 文件页数： | 135/210页 |
| 文件大小： | 2138K |
| 代理商： | OR3T80-4B600 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页当前第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页
30
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
Programmable Logic Cells (continued)
xL Routing Lines. The xL routing lines run vertically
and horizontally the height and width of the array,
respectively. There are a total of 20 xL routing lines per
PLC: ten horizontal (hxL[9:0]) and ten vertical
(vxL[9:0]). Each of the xL lines connects to the PIC
routing at either end. The xL lines are intended prima-
rily for global signals that must travel long distances
and require minimum delay and/or skew, such as
clocks or 3-state buses.
Each xL line (also called a long line) drives a buffer in
each PLC that can drive onto the horizontal and verti-
cal local clock routing segments (lCLK) in the PLC.
Also, two out of each group of ten xL segments in each
PLC can be driven by a buffer attached to a clock spine
(described later) allowing local distribution of global
clock signals. More general-purpose connections to the
long lines can be made through the xBID segments in a
PLC. Each long line is connected to an xBID segment
on a bit-by-bit basis. These BIDI connections allow cor-
ner turning from horizontal to vertical long lines, and
connection between long lines and x1 or x5 segments.
xH Routing Segments. Ten by-half (xH) routing seg-
ments run horizontally (hxH[9:0]) and ten xH routing
segments run vertically (vxH[9:0]) in each row and col-
umn in the array. These routing segments travel a dis-
tance of one-half the PLC array before being broken in
the middle of the array in the interquad area (discussed
later). They also connect at the periphery of the FPGA
to the PICs, like the xL lines. xH routing segments con-
nect to the PLCs only by switching segments. They are
intended for fast signal interconnect.
Clock (and Global CE and LSR) Routing Segments.
For a very fast and low-skew clock (or other global sig-
nal tree), clock routing segments run the entire height
and width of the PLC array. There are two clock routing
segments per PLC: one horizontal (hCLK) and one ver-
tical (vCLK). The source for these clock routing seg-
ments can be any of the I/O buffers in the PIC, the
Series 3 ExpressCLK inputs, user logic, or the pro-
grammable clock manager (PCM). The horizontal clock
routing segments (hCLK) are alternately driven by the
left and right PICs. The vertical clock routing segments
(vCLK) are alternately driven by the top and bottom
PICs.
The clock routing segments are designed to be a clock
spine. In each PLC, there is a fast connection available
from the clock segment to a long-line driver (described
earlier). With this connection, one of the clock routing
segments in each PLC can be used to drive one of the
ten xL routing segments perpendicular to it, which, in
turn, creates a clock spine tree. This feature is dis-
cussed in detail in the Clock Distribution Network sec-
tion.
Special connectivity is provided in each PLC to connect
the clock enable signals (CE and ASWE) and the LSR
signal to the clock network for fast global control signal
distribution. CE and ASWE have a special connection
to the horizontal clock spine, and LSR has a special
connection to the vertical clock spine. This allows both
signals to be routed globally within the same PLC, if
desired; however, this will consume some of the
resources available for clock signal routing.
If using these spines, the clock enable signal must
come from the right or left edge of the device, and the
LSR signal must come from the top or bottom of the
device due to their horizontal and vertical connectivity
(respectively) to the clock network.
Minimizing Routing Delay
The CIP is an active element used to connect two rout-
ing segments. As an active element, it adds signifi-
cantly to the resistance and capacitance of a routing
network (net), thus increasing the net’s delay. The
advantage of the x1 segment over an x5 segment is
routing flexibility. A net from one PLC to the next is eas-
ily routed by using x1 routing segments. As more CIPs
are added to a net, the delay increases. To increase
speed, routes that are greater than two PLCs away are
routed on the x5 routing segments because a CIP is
located only in every fifth PLC. A net that spans eight
PLCs requires seven x1 routing segments and six
CIPs. Using x5 routing segments, the same net uses
two routing segments and one CIP.
相关PDF资料 |
PDF描述 |
|---|---|
| OR3T80-5B432 | FPGA, 484 CLBS, 58000 GATES, PBGA432 |
| OR3T80-5B600 | FPGA, 484 CLBS, 58000 GATES, PBGA600 |
| OR3T80-6B432 | FPGA, 484 CLBS, 58000 GATES, PBGA432 |
| OR3T80-6B600 | FPGA, 484 CLBS, 58000 GATES, PBGA600 |
| OR3T80-4BC432 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA432 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR3T80-4BC432I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4BC600I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4PS208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4PS240I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-5BA352 | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。