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参数资料
型号： ORSO42G5-1BMN484C
厂商： Lattice Semiconductor Corporation
文件页数： 70/153页
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
23
The receive PLL has two modes of operation as follows: lock to reference and lock to data with retiming. The con-
trol bit LCKREFN_xx selects the operating mode. When setup to lock to data and no data or invalid data are
present on the HDINP and HDINN pins, the receive VCO will not lock to data and its frequency can drift outside of
the nominal ±100 ppm range. Under this condition, the receive PLL will lock to REFCLK for a xed time interval and
then will attempt to lock to receive data. The process of attempting to lock to data, then locking to clock will repeat
until valid input data exists. The default mode is lock to reference.
The recovered byte clock (RBC0) is only centered on the data when operating in the lock to data mode. In the lock
to reference mode, RBC0 is not centered on the data and may not capture the correct byte value.
The SERDES receives MSB rst and LSB last. Hence LDOUTx[7] is the bit that is received rst and LDOUTx[0] is
the bit that is received last.
8:32 DEMUX
The SERDES provides an eight bit data bus, and a clock, RBC0, which has a rising edge which occurs in the cen-
ter of the valid data region. The DEMUX block will create one 32-bit data word from the single 8-bit bus. The
DEMUX block will also provide a 77.76 MHz clock (divide-by-4 clock of RBC0) called RWCKxx to the rest of the
logic blocks such as the framer, descrambler, cell extractor and FIFOs.
Figure 9. 8:32 DEMUX Block
In the DEMUX block, LDOUTx[7:0] is demultiplexed to a 32-bit data bus synchronous to the derived 77.76 MHz
clock generated by dividing the 311.04 MHz clock by four. The 77.76 MHz clock is used by the remaining embed-
ded blocks, as well as being fed to the FPGA. Receive data from the DEMUX block is unframed. Parallel data can
be sent directly to the FPGA logic (SERDES only mode) or to the framer block for processing. Bit and byte align-
ment for the DEMUX block is shown in Figure 10.
FROM SERDES
RBC (311 MHz)
8
LDOUTx[7:0]
8:32
DEMUX
32
@ 77.76 MHz
77.76 MHz
To Framer Block
or Final Output Mux
RWCKxx
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相关代理商/技术参数
参数描述
ORSO42G5-1BMN484I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-2BM484C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-2BM484I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-2BMN484C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO42G5-2BMN484I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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