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参数资料
型号： ORT82G5-2FN680C
厂商： Lattice Semiconductor Corporation
文件页数： 56/119页
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 24
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
41
Figure 20. Receive Clocking for a Single Block (Similar Connections Would Be Used for Block B)
The receive channel alignment bypass mode allows mixing of half and full line rates among the channels, as shown
in Figure 21. The gure shows channel AC congured in full rate mode at 2.0 Gbps. Channel AD congured in half-
rate mode at 1.0 Gbps. The receive alignment FIFO per channel cannot be used in this mode.
Figure 21. Receive Clocking for Mixed Line Rates
Each SERDES block can also be congured for any line rate (0.6 to 3.7 Gbps), since each block has its own refer-
ence clock input pins.
Multi-Channel Alignment Clocking Strategies for the ORT42G5
The data on the four channels in the ORT42G5 can be independent of each other or can be synchronized in two
different ways. For example, two channels within a SERDES block can be aligned together, channel C and channel
D. Alternatively, all four channels in a SERDES block can be aligned together to form a communication channel
with a bandwidth of 10 Gbps. Individual channels within an alignment group can be disabled (i.e., powered down)
without disrupting other channels. Clocking strategies for these various modes are described in the following para-
graphs.
For dual alignment both channels must be sourced by the same clock. Either RWCKAC or RWCKAD can be con-
nected to RSYS_CLK_A2. A clocking example for dual alignment is shown in Figure 22.
Common Logic, Block A
Channel AC
Channel AD
REFCLK[P:N]_A
2
156.25 MHz
RCK78A
RWCKAC
RWCKAD
RSYS_CLK_A2
FPGA
Logic
Two Channels of
3.125 Gbps
Incoming Serial Data
78.125 MHz
All Recovered
Clocks at
78.125 MHz
Common Logic, Block A
Channel AC
Channel AD
REFCLK[P:N]_A
2
100 MHz
RCK78A
RWCKAC
FPGA
Logic
One Channel of
2.0 Gbps (Full-Rate)
and One Channel of
1.0 Gbps (Half-Rate)
Incoming Serial Data
25 MHz
RWCKAD
25 MHz
or 50 MHz
50 MHz
RSYS_CLK_A2
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相关代理商/技术参数
参数描述
ORT82G5-2FN680C1 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-2FN680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-2FN680I1 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-3BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-3BM680C2 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs
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