- 您现在的位置：买卖IC网 > PDF目录11733 > ORT82G5-2FN680C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPBGA PDF资料下载
参数资料
| 型号： | ORT82G5-2FN680C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 88/119页 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 24 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页当前第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
70
SERDES Global Control Registers (Read Write) Act on all Four Channels in SERDES Quad A or SERDES Quad B.
30005 - A
30105 - B
[0]
Reserved
See
bit
descrip.
Reserved, must be set to 0. Set to 0 on device reset.
[1]
GMASK_[A:B]
Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms
of all channels in the SERDES quad are prevented from generating an
interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit over-
rides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset.
[2]
GSWRST_[A:B]
Software reset bit. The GSWRST_[A:B] bit provides the same function
as the hardware reset for the transmit and receive sections of all four
channels, except that the device conguration settings are not affected
when GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once
set, this bit must be manually set and cleared. The GSWRST_[A:B] bit
overrides the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device
reset.
[3]
GPWRDNT_[A:B]
Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of
the transmit hardware for all four channels of are powered down to con-
serve power. The GPWRDNT_[A:B] bit overrides the individual
PWRDNT_xx bits. GPWRDNT_[A:B] = 0 on device reset.
[4]
GPWRDNR_[A:B]
Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of
the receive hardware for all four channels are powered down to conserve
power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx
bits. GPWRDNR_[A:B] = 0 on device reset.
[5]
Reserved
Reserved, 1 on device reset.
[6]
Not used
Not used. 0 on reset.
[7]
GTESTEN_[A:B]
Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and
receive sections of all four channels are placed in test mode. The
GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits.
GTESTEN_[A:B] = 0 on device reset.
30006 - A
30106 - B
[0:4]
TestMode[A:B]
00
TestMode - See Test Mode section for settings
[5]
Not used
[6:7]
Reserved
Control Registers (Read/Write), xx=[AA,...,BD]
30800 - Ax
30900 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
ENBYSYNC_xx
00
ENBYSYNC_xx = 1 Enables Receiver Byte Synchronization for Channel
xx. ENBYSYNC_xx = 0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
LCKREFN_xx
LCKREFN_xx = 0 Locks the receiver PLL to ref reference clock for
Channel xx.
LCKREFN_xx =1 = Locks the receiver to data for Channel xx.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xx = 0 on device reset.
30801 - Ax
30901 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
LOOPENB_xx
Enable Loopback Mode for Channel xx. When LOOPEN_xx=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xx=0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
NOWDALIGN_xx
Word Align Disable Bit. When NOWDALIGN_xx=1, receiver word align-
ment is disabled for Channel xx. NOWDALIGN_xx=0 on device reset.
Table 30. ORT82G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
相关PDF资料 |
PDF描述 |
|---|---|
| MSP430F4793IPZ | IC MCU 16BIT 60KB FLASH 100LQFP |
| VE-J4B-IW-F3 | CONVERTER MOD DC/DC 95V 100W |
| PIC18F4510-I/ML | IC MCU FLASH 16KX16 44QFN |
| VE-J4B-IW-F2 | CONVERTER MOD DC/DC 95V 100W |
| PIC32MX675F256L-80I/PF | IC MCU 32BIT 256KB FLASH 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-2FN680C1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2FN680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 3.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2FN680I1 | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-3BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-3BM680C2 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs |
发布紧急采购，3分钟左右您将得到回复。