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| 型号： | P0304 |
| 厂商： | Terasic Technologies Inc |
| 文件页数： | 44/93页 |
| 文件大小： | 0K |
| 描述： | DE2-70 CALL FOR ACADEMIC PRICING |
| 标准包装： | 1 |
| 类型： | FPGA |
| 适用于相关产品： | Cyclone II 2C70 |
| 所含物品： | DE2-70 板，电源，线缆，塑料盖和软件 |
| 配用： | P0033-ND - BOARD ADAPTER HSMC TO GPIO P0006-ND - BOARD ADAPTER THDB-SUM P0001-ND - MODULE DIGITAL CAMERA 5MP (D5M) P0307-ND - KIT DEV 4.3" LCD TOUCH PANEL |
| 相关产品： | 544-2147-ND - IC CYCLONE II FPGA 70K 896-FBGA 544-2146-ND - IC CYCLONE II FPGA 70K 896-FBGA 544-2145-ND - IC CYCLONE II FPGA 70K 896-FBGA 544-2144-ND - IC CYCLONE II FPGA 70K 896-FBGA 544-2143-ND - IC CYCLONE II FPGA 70K 672-FBGA 544-2142-ND - IC CYCLONE II FPGA 70K 672-FBGA 544-2141-ND - IC CYCLONE II FPGA 70K 672-FBGA 544-2140-ND - IC CYCLONE II FPGA 70K 672-FBGA 544-1696-ND - IC CYCLONE II FPGA 70K 896-FBGA 544-1695-ND - IC CYCLONE II FPGA 70K 896-FBGA 更多... |
| 其它名称： | DE2-70 |
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DE2-70 User Manual
LCD_DATA[5]
LCD_DATA[6]
LCD_DATA[7]
LCD_RW
LCD_EN
LCD_RS
LCD_ON
LCD_BLON
PIN_C2
PIN_C3
PIN_B2
PIN_F3
PIN_E2
PIN_F2
PIN_F1
PIN_G3
LCD Data[5]
LCD Data[6]
LCD Data[7]
LCD Read/Write Select, 0 = Write, 1 = Read
LCD Enable
LCD Command/Data Select, 0 = Command, 1 = Data
LCD Power ON/OFF
LCD Back Light ON/OFF
Table 5.6. Pin assignments for the LCD module.
Note that the current LCD modules used on DE2/DE2-70 boards do not have backlight. Therefore
the LCD_BLON signal should not be used in users’ design projects.
5.6 Using the Expansion Header
The DE2-70 Board provides two 40-pin expansion headers. Each header connects directly to 36
pins of the Cyclone II FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC33), and two
GND pins. Among these 36 I/O pins, 4 pins are connected to the PLL clock input and output pins of
the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA.
The voltage level of the I/O pins on the expansion headers can be adjusted to 3.3V, 2.5V, or 1.8V
using JP1. Because the expansion I/Os are connected to the BANK 5 of the FPGA and the VCCIO
voltage (VCCIO5) of this bank is controlled by the header JP1, users can use a jumper to select the
input voltage of VCCIO5 to 3.3V, 2.5V, and 1.8V to control the voltage level of the I/O pins. Table
5.7 lists the jumper settings of the JP1. The pin-outs of the JP1 appear in the Figure 5.10.
Finally, Figure 5.11 shows the related schematics. Each pin on the expansion headers is connected
to two diodes and a resistor that provide protection from high and low voltages. The figure shows
the protection circuitry for only two of the pins on each header, but this circuitry is included for all
72 data pins. Table 5.8 gives the pin assignments.
IO Voltage of Expansion
JP1 Jumper Settings
Supplied Voltage to VCCIO5
Headers (J4/J5)
Short Pins 1 and 2
Short Pins 3 and 4
Short Pins 5 and 6
1.8V
2.5V
3.3V
1.8V
2.5V
3.3V
Table 5.7. Voltage level setting of the expansion headers using JP1.
41
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