参数资料
型号: P0304
厂商: Terasic Technologies Inc
文件页数: 78/93页
文件大小: 0K
描述: DE2-70 CALL FOR ACADEMIC PRICING
标准包装: 1
类型: FPGA
适用于相关产品: Cyclone II 2C70
所含物品: DE2-70 板,电源,线缆,塑料盖和软件
配用: P0033-ND - BOARD ADAPTER HSMC TO GPIO
P0006-ND - BOARD ADAPTER THDB-SUM
P0001-ND - MODULE DIGITAL CAMERA 5MP (D5M)
P0307-ND - KIT DEV 4.3" LCD TOUCH PANEL
相关产品: 544-2147-ND - IC CYCLONE II FPGA 70K 896-FBGA
544-2146-ND - IC CYCLONE II FPGA 70K 896-FBGA
544-2145-ND - IC CYCLONE II FPGA 70K 896-FBGA
544-2144-ND - IC CYCLONE II FPGA 70K 896-FBGA
544-2143-ND - IC CYCLONE II FPGA 70K 672-FBGA
544-2142-ND - IC CYCLONE II FPGA 70K 672-FBGA
544-2141-ND - IC CYCLONE II FPGA 70K 672-FBGA
544-2140-ND - IC CYCLONE II FPGA 70K 672-FBGA
544-1696-ND - IC CYCLONE II FPGA 70K 896-FBGA
544-1695-ND - IC CYCLONE II FPGA 70K 896-FBGA
更多...
其它名称: DE2-70
DE2-70 User Manual
the user clicks on the Clear button in the window panel of the software driver, the host computer
sends a different USB packet to the board, which causes the Nios II processor to clear the hardware
counter to zero.
Figure 6.7. Block diagram of the USB device demonstration.
Demonstration Setup, File Locations, and Instructions
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Project directory: DE2_70_NIOS_DEVICE_LED\HW
Bit stream used: DE2_70_NIOS_DEVICE_LED.sof
Nios II Workspace: DE2_70_NIOS_DEVICE_LED\HW\Software
Borland BC++ Software Driver: DE2_70_NIOS_DEVICE_LED\SW
Connect the USB Device connector of the DE2-70 board to the host computer using a USB
cable (type A ? B).
Load the bit stream into FPGA
Run Nios II IDE with HW as the workspace. Click on Compile and Run
A new USB hardware device will be detected . Specify the location of the driver as
DE2 _ 70_NIOS_DEVICE_LED\D12test.inf (Philips PDIUSBD12 SMART Evaluation
Board). Ignore any warning messages produced during installation
The host computer should report that a Philips PDIUSBD12 SMART Evaluation Board is
now installed
Execute the software: DE2 _ 70_NIOS_DEVICE_LED\SW\ISP1362DcUsb.exe on the host
computer. Then, experiment with the software by clicking on the ADD and Clear buttons
Figure 6.8 illustrates the setup for this demonstration.
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