参数资料
型号: P83C280
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42
封装: 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件页数: 49/84页
文件大小: 420K
代理商: P83C280
1997 Dec 12
49
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
17.5
DDC2AB/DDC2B+ protocol
DDC2AB/DDC2B+ is a superset of DDC2B. Monitors that
implement DDC2AB/DDC2B+ are full featured
ACCESS.bus devices. Essentially, they are similar to
DDC2B. The I
2
C-bus interface forms the fundamental
layer for both protocols. However, in DDC2AB/DDC2B+
the default address for monitors is assigned to 6EH
instead of A0H and A1H in DDC2B. Monitors and hosts
can play both the roles of master and slave. Under this
kind of protocol, it is easy to extend the support for hosts
to read VESA Video Display Information Format (VDIF)
and remotely control monitor functions.
The read/write protocols can be the same as described in
Section 17.4.
Nevertheless, the command/information sequence
between host and monitor must conform to the
specification of ACCESS.bus.
Timing rules specified in ACCESS.bus such as maximum
response time to RESET message (<250 ms) from host,
maximum time to hold SCL LOW (<2 ms) etc., can be
satisfied through software checks and built-in timers such
as Timer 0 and Timer 1 in the P83C880. In
DDC2AB/DDC2B+ the monitor itself can act as a master to
activate the transaction. The default address assigned for
the host is 50H.
Figure 26 shows the overview and relationship between
software and the existing I
2
C-bus hardware for the DDC
interface.
Fig.26 The conceptual structure of the DDC interface.
handbook, full pagewidth
MGG035
DDC INTERRUPT
VECTOR ADDRESS
(002BH)
MODE = 1
CHECK MODE FLAG IN DDCCON
MODE = 0
DDC2B
+
/DDC2AB
COMMAND
RECEIVED
DDC2B
COMMAND
RECEIVED
DDC2B
+
/DDC2AB
UTILITIES
DDC2B
UTILITIES
I
2
C-BUS
SERVICE ROUTINES
DDC1
UTILITIES
I
2
C-BUS INTERFACE
(HARDWARE)
DDC1 TRANSMITTER
(HARDWARE)
SWENB = 0
SWENB = 1
相关PDF资料
PDF描述
P83C380 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
P87C380 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
P83C880 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
P83C180 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
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