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参数资料
| 型号： | P83C576EHPN |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40 |
| 文件页数： | 10/46页 |
| 文件大小： | 447K |
| 代理商： | P83C576EHPN |
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Philips Semiconductors
Product specification
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
1998 Jun 04
10
PRE2
PRE1
PRE0
LVRE
OFRE
DPD
WDRUN
WDMOD
WDCON
(C4H)
SHADOW REGISTER
FOR WDCON
WATCHDOG FEED
SMOD1
SMOD0
OSF
LVF
WDTOF
PD
IDL
PCON
(87H)
OSC FREQ BELOW OSCF
(MIN FREQUENCY)
RST
+
–
V
CC
VLOW
(LOW V
REFERENCE)
POWER-ON DETECT
PCA WATCHDOG
WATCHDOG TIMER
8xC576
RESET
POF
SU00515B
CIDL
WDTE
–
–
–
CPS1
CPS0
ECF
CMOD
(D9H)
–
–
–
SRST
TXI
LO
AO
AUXR
(8EH)
–
SHADOW REGISTER
WDTE
Figure 1.
Reset Circuitry
TIMERS
The 8XC576 has four on-chip timers.
Timers 0 and 1 are identical in every way to Timers 0 and 1 on the
80C51.
Timer 2 on the 8XC576 is identical to the 80C52 Timer 2 (described
in detail in the 80C52 overview) with the exception that it is an up or
down counter. To configure the Timer to count down the DCEN bit in
the T2MOD special function register must be set and a low level
must be present on the T2EX pin (P1.1).
The Pulse Width Modulator (PWM) system can be used as a timer
by disabling its outputs and monitoring its counter overflow flag, the
PWMF bit in the PWCON register (see the PWM section for details).
The Watchdog timer operation and implementation is similar to the
8XC550 (for additional information see the 8XC550 datasheet) with
the exception that the reset values of the WDCON and WDL special
function registers have been changed. The changes in these
registers cause the watchdog timer to be enabled with a timeout of
16384
×
T
OSC
when the part is reset. The watchdog can be disabled
by executing a valid feed sequence and then clearing WDRUN (bit 2
in the WDCON SFR). In timer mode, the timer is controlled by
toggling the WDRUN bit. The timeout flag, WDTOF, is set when the
timer overflows and must be cleared in software.
PROGRAMMABLE COUNTER ARRAY (PCA)
The Programmable Counter Array is a special Timer that has five
16-bit capture/compare modules associated with it. Each of the
modules can be programmed to operate in one of four modes: rising
and/or falling edge capture, software timer, high-speed output, or
pulse width modulator. Each module has a pin associated with it in
port 2. Module 0 is connected to P2.0(CEX0), module 1 to
P2.1(CEX1), etc. The basic PCA configuration is shown in Figure 2.
The PCA timer is a common time base for all five modules and can
be programmed to run at: 1/12 the oscillator frequency, 1/4 the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin
(P2.7). The timer count source is determined from the CPS1 and
CPS0 bits in the CMOD SFR as follows (see Figure 3):
CPS1 CPS0 PCA Timer Count Source
0
0
1/12 oscillator frequency
0
1
1/4 oscillator frequency
1
0
Timer 0 overflow
1
1
External Input at ECI pin (P2.7)
In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function on
module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 3.
The watchdog timer function is implemented in module 4 as
implemented in other parts that have a PCA that are available on the
market. However, if a watchdog timer is required in the target
application, it is recommended to use the hardware watchdog timer
that is implemented on the 87C576 separately from the PCA (see
Figure 15).
The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and each module (refer to Figure 6). To
run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
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| P87C576EHPN | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
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