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| 型号： | P83C576EHPN |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40 |
| 文件页数： | 30/46页 |
| 文件大小： | 447K |
| 代理商： | P83C576EHPN |
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Philips Semiconductors
Product specification
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
1998 Jun 04
30
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C, –40
°
C to +85
°
C, and –40
°
C to +125
°
C; V
CC
= 5V
±
10%, V
SS
= 0V
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1
MAX
UNIT
V
IL
Input low voltage (except Port 1, EA)
–0.5
0.2V
CC
–0.1
V
V
IL1
Input low voltage (EA)
–0.5
0.2V
CC
–0.45
V
V
IL2
Input low voltage (Port 1)
–0.5
0.3V
CC
V
V
IH
Input high voltage (except Port 1, XTAL1, RST)
I
IH
< 2mA
0.2V
CC
+0.9
V
CC
+0.5
V
V
IH1
Input high voltage (XTAL1, RST, Port 1)
I
IH
< 2mA
0.7V
CC
V
CC
+0.5
V
HYS
Hysteresis voltage (Port 1)
200
mV
V
OL
Output voltage low (Ports 1, 2, 3)
I
OL
= 1.6mA
0.45
V
V
OL1
Output voltage low (Ports 0, ALE, PSEN
)
I
OL
= 3.2mA
0.45
V
V
OH
Output voltage high (Ports 1, 2, 3 in push-pull mode)
I
OH
= –1.6mA
V
CC
–1.0
V
V
OH1
Output voltage high (Port 0, ALE, PSEN)
I
OH
= –3.2mA
V
CC
–0.7
V
V
OH2
Output voltage high in weak pullup mode (Port 0, 2, 3)
I
OH
= –10
μ
A
V
CC
–1.0
V
V
IO
Offset voltage comparator inputs
–35
+35
mV
V
CR
Common mode range comparator inputs
0
V
CC
V
I
IL
Logical 0 input current (Ports 0, 2, 3) (weak pull-up)
V
IN
= 0.45V
–250
μ
A
I
IH
Input pulldown current (Port 0, Port2 in open drain mode)
0.45 < V
IN
< V
CC
2
40
μ
A
I
L2
Input leakage current (EA, P0. 2. 3 High-Z)
0.45 < V
IN
< V
CC
–10
+10
μ
A
I
LA
Input leakage current comparator/ADC inputs
0 < V
IN
< V
CC
–1.0
+1.0
μ
A
I
CC
Power supply current:
7
Active mode @ 16MHz
5
Idle mode @ 16MHz
Power-down mode
See note 6
20
8
5
30
12
75
mA
mA
μ
A
R
RST
Internal reset pull-up resistor
V
IN
= 0V
50
200
k
V
LOW
Low V
CC
detect voltage
Pin capacitance
9
3.75
4.25
V
C
IO
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9V
CC
specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
is between V
and V
.
5. I
MAX at other frequencies can be determined from Figure 33.
6. See Figures 34 through 37 for I
CC
test conditions.
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
10mA
Maximum I
per 8-bit port:
26mA
Maximum total I
OL
for all outputs:
71mA
If I
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. 20pF MAX for CERDIP package; 15pF MAX for all other packages.
f = 1MHz
15
pF
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