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| 型号： | P83C576EHPN |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40 |
| 文件页数： | 26/46页 |
| 文件大小： | 447K |
| 代理商： | P83C576EHPN |
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Philips Semiconductors
Product specification
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
1998 Jun 04
26
1/2
PWMP
REG
8-BIT
PRESCALER
8-BIT
UP
COUNTER
8-BIT
DETECT
OUTPUT
BUFFER
PWM0
PWM1
8-BIT
DETECT
OUTPUT
BUFFER
f
OSC
INTERNAL
BUS
P2.6
P2.7
SU00256A
Figure 23.
Block Diagram of PWMs
PCA Interrupt System
The PCA on most 80C51 family devices provides a single interrupt
source, EC (IE.6). The 8xC576 expands the flexibility of the PCA by
providing additional interrupt sources for each of the five PCA
modules, EC0 (IE1.0) through EC4 (IE1.4), in addition to the original
interrupt source EC (IE.6). Any of these sources can be enabled at
any time. It is possible for both a module source (EC0 through EC4)
to be enabled at the same time that the single source, EC, is
enabled. In this case, a module event will generate an interrupt for
both the module source and the single source, EC.
Priority Source
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Flag
IE0
ADF
TF0
IE1
TF1
RI,TI
CC0
CC1
CC2
CC3
CC4
ECF
TF2/EXF2
IBF
OBE
Vector
03H
3BH
0BH
13H
1BH
23H
43H
4BH
53H
5BH
63H
33H
2BH
6BH
73H
INT0
ADC
TIMER 0
INT1
TIMER 1
SERIAL
PCA0
PCA1
PCA2
PCA3
PCA4
PCA
TIMER 2
UPI
UPI
highest priority
lowest priority
Power Control (PCON) Register
SMOD1
PCON.7
SMOD0
PCON.6
OSF
PCON.5
POF
PCON.4
LVF
PCON.3
WDTOF
PCON.2
PD
PCON.1
IDL
PCON.0
double baud rate bit
SCON.7 access control
oscillator fail flag
power off flag
low voltage flag
watchdog timeout flag
power down mode bit
idle mode bit
UNIVERSAL PERIPHERAL INTERFACE
UPI mode allows the 8XC576 to function as a slave processor
connected to a host CPU bus via port 0. The interface consists of
port 0 input and output buffer registers and the UPI control/status
register (UCS). UPI mode is enabled by setting the UPI enable bit
(UE) in the UCS. When operating in UPI mode, port 0 pins should
be programmed to High-Z (P0M1=1 and P0M2=0) by user firmware.
Access to port 0 is controlled by inputs WR, RD, CS, and A0. RD
and WR are the external read and write strobes controlled by the
host CPU. CS is the chip select input, normally a decoded address
from the host CPU bus, which qualifies RD and WR (these pins
have no effect when CS=1). The A0 pin is an address input from the
host CPU which selects either the port 0 output buffer or the UCS
register to be output during a read operation. During a write
operation, the value of the A0 pin is latched in the AF flag in the
UCS register. The following is a summary of the UPI data control
inputs:
CS
0
RD
0
WR
1
A0
0
read port 0 output buffer,
clear OBF/set OBE
read UPI control/ status register
write data to input buffer set IBF, clear AF
write command to input buffer set IBF, AF
disable input/output
0
0
0
1
0
1
1
x
1
0
0
x
1
0
1
x
UPI Control Status Register
UCS.7
ST7
UCS.6
ST6
UCS.5
ST5
UCS.4
ST4
UCS.3
UE
(UCS, Reset value = 00H)
User defined status bit
User defined status bit
User defined status bit
User defined status bit
UPI Enable bit – if UE=1, UPI is enabled
(read only AF, IBF, and OBE/OBF), if UE=0,
UPI is disabled and port 0 functions
normally.
Address Flag – contains status of the A0
(address) pin during the last write. If A0=0,
the input buffer should be interpreted as
data by the 8XC576 software, if A0=1, the
input buffer should be interpreted as a
command.
Input Buffer Full flag – set by hardware on
trailing (rising) edge of WR when CS=0,
cleared by hardware when port 0 SFR is
read (by the 8XC576 software).
Output Buffer Full flag – set by hardware
during writes (by 8XC576 software) to the
port 0 SFR, set/cleared by hardware on the
trailing (rising) edge of RD when CS=0 and
A0=0.
UCS.2
AF
USC.1
IBF
USC.0
OBE/OBF
NOTE:
This bit is defined as OBE (1=empty) when read by the
MCU, and, as OBF (—full) when read by the external host.
The IBF and OBF flag bits reflect the status of the input/output
buffers. The host CPU writes to the 8XC576 by driving data on the
external bus connected to port 0 and strobing the WR pin while
CS=0. The WR strobe latches port 0 data in the input buffer and
sets the IBF flag on the trailing (rising) edge. When the 8XC576
reads from port 0 in UPI mode, it reads from the input buffer and
相关PDF资料 |
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| P87C576EHPN | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P83C576EBBB | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P87C576EBBB | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
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| P83C576EBPN | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
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