- 您现在的位置：买卖IC网 > PDF目录367728 > P83C576EHPN (NXP SEMICONDUCTORS) 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer PDF资料下载
参数资料
| 型号： | P83C576EHPN |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40 |
| 文件页数： | 27/46页 |
| 文件大小： | 447K |
| 代理商： | P83C576EHPN |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页
Philips Semiconductors
Product specification
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
1998 Jun 04
27
clears the IBF. When the 8XC576 writes to port 0 in UPI mode, it
writes to the output buffer which sets the OBF and clears the OBE
flag. The host CPU can read the output buffer or the UCS register
enabling the port 0 drivers, the OBF flag is cleared and the OBE flag
is set when the output buffer is read.
When the UPI is enabled, the AF, IBF, and OBE/OBF flags are
read-only, and thus can only be modified by specific hardware
events.
The UPI runs in idle mode. It can interrupt the part out of Idle mode
for all UPI write and data read operations. It will not interrupt out of
idle mode for a UCS register read operation.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 4.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset. Also see UPI section.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. The control
bits for the reduced power modes are in the special function register
PCON. Power-down mode can be terminated with either a hardware
reset or external interrupt. With an external interrupt INT0 or INT1
must be enabled and configured as level sensitive. Holding the pin
low restarts to oscillator and bringing the pin back high completes
the exit.
Power-down mode can be disabled by the DPD bit in the WDCON
register. Reset and waking up from power-down will also enable the
DPD bit, therefore, the DPD bit must be cleared again before the
power-down mode.
DESIGN CONSIDERATIONS
At power-on, the voltage on V
CC
must come up with RST low for a
proper start-up.
Table 2 shows the state of I/O ports during low current operating
modes.
Table 2. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
相关PDF资料 |
PDF描述 |
|---|---|
| P87C576EHPN | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P83C576EBBB | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P87C576EBBB | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P87C576EBAA | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P83C576EBPN | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
相关代理商/技术参数 |
参数描述 |
|---|---|
| P83C591 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller with CAN controller |
| P83C591SFA | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller with CAN controller |
| P83C591SFB | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller with CAN controller |
| P83C591VFA | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller with CAN controller |
| P83C591VFB | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller with CAN controller |
发布紧急采购，3分钟左右您将得到回复。