参数资料
型号: P89LPC9107FDH,129
厂商: NXP Semiconductors
文件页数: 10/39页
文件大小: 0K
描述: IC 80C51 MCU FLASH 1K 14-TSSOP
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 960
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: UART/USART
外围设备: 欠压检测/复位,LED,POR,PWM,WDT
输入/输出数: 12
程序存储器容量: 1KB(1K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1003-ND - KIT FOR LCD DEMO
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-2002-5
935278497129
P89LPC9107FDH-S
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P89LPC9102_9103_9107_3
NXP
B
.V
.2007.
All
r
ights
reser
v
ed.
Pr
oduct
data
sheet
Re
v
.03
10
J
u
ly
2007
18
of
61
NXP
Semiconductor
s
P89LPC9102/9103/9107
8-bit
micr
ocontr
oller
s
with
tw
o-c
loc
k
accelerated
80C51
core
[1]
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specied, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
[2]
All ports are in input-only (high-impedance) state after power-up.
[3]
The RSTSRC register reects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source ags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
[4]
The only reset source that affects these SFRs is power-on reset.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1s, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog timer reset and is logic 0 after power-on
reset. Other resets will not affect WDTOF.
RSTSRC
Reset source register
DFH
-
BOF
POF
-
R_WD
R_SF
R_EX
RTCCON
Real-time clock control
D1H
RTCF
RTCS1
RTCS0
-
ERTC
RTCEN
011x xx00
RTCH
Real-time clock register high
D2H
0000 0000
RTCL
Real-time clock register low
D3H
0000 0000
SP
Stack pointer
81H
07
0000 0111
TAMOD
Timer 0 and 1 auxiliary mode
8FH
-
T1M2
-
T0M2
00
xxx0 xxx0
Bit address
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer 0 and 1 control
88H
TF1
TR1
TF0
TR0
----
00
0000 0000
TH0
Timer 0 high
8CH
00
0000 0000
TH1
Timer 1 high
8DH
00
0000 0000
TL0
Timer 0 low
8AH
00
0000 0000
TL1
Timer 1 low
8BH
00
0000 0000
TMOD
Timer 0 and 1 mode
89H
-
T1M1
T1M0
-
T0M1
T0M0
00
0000 0000
TRIM
Internal oscillator trim register
96H
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Table 7.
P89LPC9102 special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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