参数资料
型号: P89LPC9107FDH,129
厂商: NXP Semiconductors
文件页数: 24/39页
文件大小: 0K
描述: IC 80C51 MCU FLASH 1K 14-TSSOP
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 960
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: UART/USART
外围设备: 欠压检测/复位,LED,POR,PWM,WDT
输入/输出数: 12
程序存储器容量: 1KB(1K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1003-ND - KIT FOR LCD DEMO
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-2002-5
935278497129
P89LPC9107FDH-S
P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
30 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
8.11.1 External interrupt inputs
The P89LPC9102/9103/9107 has a Keypad Interrupt function. This can be used as an
external interrupt input.
If enabled when the P89LPC9102/9103/9107 is put into Power-down mode or Idle mode,
the interrupt will cause the processor to wake-up and resume operation. Refer to Section
Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC9102)
002aaa976
BOF
EBO
KBIF
EKBI
interrupt
to CPU
wake-up
(if in power-down)
EWDRT
CMF
EC
EA (IE0.7)
RTCF
ERTC
(RTCCON.1)
WDOVF
TF1
ET1
TF0
ET0
ENADCI1
ADCI1
ENBI1
BNDI1
EAD
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