参数资料
型号: P89LPC9107FDH,129
厂商: NXP Semiconductors
文件页数: 20/39页
文件大小: 0K
描述: IC 80C51 MCU FLASH 1K 14-TSSOP
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 960
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: UART/USART
外围设备: 欠压检测/复位,LED,POR,PWM,WDT
输入/输出数: 12
程序存储器容量: 1KB(1K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: DB-TSSOP-LPC9107-ND - BOARD FOR LPC9107 TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1003-ND - KIT FOR LCD DEMO
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-2002-5
935278497129
P89LPC9107FDH-S
P89LPC9102_9103_9107_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 10 July 2007
27 of 61
NXP Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.2 Enhanced CPU
The P89LPC9102/9103/9107 uses an enhanced 80C51 CPU which runs at six times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.3 Clocks
8.3.1 Clock denitions
The P89LPC9102/9103/9107 device has internal clocks as dened below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of the clock
be optionally divided to a slower frequency (see Section 8.8 “CCLK modication: DIVM
Note: fosc is dened as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.
PCLK — Clock for the various peripheral devices and is CCLK
2.
8.3.2 CPU clock (CCLK)
The P89LPC9102/9103/9107 provides user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are congured when the ash memory is programmed and
include an on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock
input.
8.4 On-chip RC oscillator option
The P89LPC9102/9103/9107 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz
± 1 % at room
temperature. End-user applications can write to the Trim register to adjust the on-chip RC
oscillator to other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1)
the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
The RCCLK bit (TRIM.7) can be used to switch between the clock source selected by
UCFG1 and the internal RC oscillator. This allows a low frequency source such as the
WDT or low speed external source to clock the device in order to save power and then
switch to the higher speed internal RC oscillator to perform processing.
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