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参数资料
| 型号： | P89LPC9361FDH,518 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 2/94页 |
| 文件大小： | 0K |
| 描述： | IC MCU 80C51 16KB FLASH 28TSSOP |
| 标准包装： | 1 |
| 系列： | LPC900 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 18MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，温度传感器，WDT |
| 输入/输出数： | 26 |
| 程序存储器容量： | 16KB（16K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 数据转换器： | A/D 8x8b; D/A 2x8b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
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P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
10 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
P2.0 to P2.7
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
7.16.1 “Port configurations” and Table 12 “Static characteristics” for details.
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0/ICB/DAC0
/AD03
1I/O
P2.0 — Port 2 bit 0.
I
ICB — Input Capture B. (P89LPC9351/9361)
O
DAC0 — Digital-to-analog converter output.
I
AD03 — ADC0 channel 3 analog input.
P2.1/OCD/AD02
2
I/O
P2.1 — Port 2 bit 1.
O
OCD — Output Compare D. (P89LPC9351/9361)
I
AD02 — ADC0 channel 2 analog input.
P2.2/MOSI
13
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input.
P2.3/MISO
14
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — When configured as master, this pin is input, when configured as slave,
this pin is output.
P2.4/SS
15
I/O
P2.4 — Port 2 bit 4.
I
SS — SPI Slave select.
P2.5/SPICLK
16
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6/OCA
27
I/O
P2.6 — Port 2 bit 6.
O
OCA — Output Compare A. (P89LPC9351/9361)
P2.7/ICA
28
I/O
P2.7 — Port 2 bit 7.
I
ICA — Input Capture A. (P89LPC9351/9361)
P3.0 to P3.1
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
7.16.1 “Port configurations” and Table 12 “Static characteristics” for details.
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
9I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the flash configuration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).
It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the RTC/system timer.
Table 3.
Pin description …continued
Symbol
Pin
Type Description
PLCC28,
TSSOP28
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