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参数资料
| 型号： | P89LPC9361FDH,518 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 41/94页 |
| 文件大小： | 0K |
| 描述： | IC MCU 80C51 16KB FLASH 28TSSOP |
| 标准包装： | 1 |
| 系列： | LPC900 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 18MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，温度传感器，WDT |
| 输入/输出数： | 26 |
| 程序存储器容量： | 16KB（16K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 数据转换器： | A/D 8x8b; D/A 2x8b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
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P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
46 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.23.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
7.23.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SnBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
7.23.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated
when the double buffer is ready to receive new data.
7.23.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TI interrupt.
If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be
double-buffered together with SBUF data.
7.24 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I2C-bus may be used for test and diagnostic purposes.
device provides a byte-oriented I2C-bus interface that supports data transfers up to
400 kHz.
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| P89LPC936FA | 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 16K FLASH PLCC28 |
| P89LPC936FA,529 | 功能描述:8位微控制器 -MCU 80C51 16K FL 768B RM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC936FA529 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ LCC-28 |
| P89LPC936FDH | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs |
| P89LPC936FDH,518 | 功能描述:8位微控制器 -MCU 16K FL/768B RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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