参数资料
型号: P89LPC9361FDH,518
厂商: NXP Semiconductors
文件页数: 60/94页
文件大小: 0K
描述: IC MCU 80C51 16KB FLASH 28TSSOP
标准包装: 1
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 26
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x8b; D/A 2x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
包装: 标准包装
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
63 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
in result register, ADxDAT1. The first channel is again converted and its result stored in
ADxDAT2. The second channel is again converted and its result placed in ADxDAT3. An
interrupt is generated, if enabled, after every set of four conversions (two conversions per
channel).
In P89LPC9351/9361, in dual channel mode, the PGA channel selection is independent
and can be different to A/D conversion channel selection. If different, the gain of the
selected ADC channel is 1.
8.6.6 Single step mode
This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any
combination of the four input channels can be selected for conversion. After each channel
is converted, an interrupt is generated, if enabled, and the A/D waits for the next start
condition. May be used with any of the start modes.
In P89LPC9351/9361, in single step mode, the PGA channel selection is independent and
can be different to A/D conversion channel selection. If different, the gain of the selected
ADC channel is 1.
8.7 Conversion start modes
8.7.1 Timer triggered start
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,
additional Timer 0 triggers are ignored until the conversion has completed. The Timer
triggered start mode is available in all ADC operating modes.
8.7.2 Start immediately
Programming this mode immediately starts a conversion. This start mode is available in all
ADC operating modes.
8.7.3 Edge triggered
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has
started, additional edge triggers are ignored until the conversion has completed. The edge
triggered start mode is available in all ADC operating modes.
8.7.4 Dual start immediately
Programming this mode starts a synchronized conversion of both A/D converters. This
start mode is available in all A/D operating modes. Both A/D converters must be in the
same operating mode. In the continuous conversion modes, both A/D converters must
select an identical number of channels. Any trigger of either A/D will start a simultaneous
conversion of both A/Ds.
8.8 Boundary limits interrupt
Each of the A/D converters has both a high and low boundary limit register. The user may
select whether an interrupt is generated when the conversion result is within (or equal to)
the high and low boundary limits or when the conversion result is outside the boundary
limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt
criteria. The boundary limit may be disabled by clearing the boundary limit interrupt
enable.
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