- 您现在的位置：买卖IC网 > PDF目录367725 > P8xCL580HFT (NXP Semiconductors N.V.) Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC PDF资料下载
参数资料
| 型号： | P8xCL580HFT |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| 中文描述： | 低电压8 - UART的，位微控制器的I2C总线和ADC |
| 文件页数： | 26/80页 |
| 文件大小： | 366K |
| 代理商： | P8XCL580HFT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
1997 Mar 14
26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I
2
C-bus and ADC
P80CL580; P83CL580
14.4
Status of external pins
The status of the external pins during Idle and Power-down
mode is shown in Table 13. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.
If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor ‘p1’;
see Fig.9(a).
Table 13
Status of external pins during Idle and Power-down modes
14.5
Power Control Register (PCON)
Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressable, the reset value of
PCON is 0XX00000B.
Table 14
Power Control Register (address 87H)
Table 15
Description of PCON bits
MODE
MEMORY
ALE
PSEN
PWM0
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
Idle
internal
external
internal
external
1
1
0
0
1
1
0
0
active
active
HIGH
HIGH
port data
floating
port data
floating
port data
port data
port data
port data
port data
address
port data
port data
port data
port data
port data
port data
port data
port data
port data
port data
Power-down
7
6
5
4
3
2
1
0
SMOD
WLE
GF1
GF0
PD
IDL
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double Baud rate bit
. When set to a logic 1 the baud rate is doubled when the serial
port SIO0 is being used in modes 1, 2 or 3.
Reserved.
Watchdog Load Enable
. This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when T3 is loaded.
GF1 and GF0
General purpose flag bits
.
PD
Power-down bit
. Setting this bit activates the Power-down mode. This bit can only be
set if input EWN is HIGH. If a logic 1 is written to both PD and IDL at the same time, PD
takes precedence.
IDL
Idle mode bit
. Setting this bit activates the Idle mode.
6 and 5
4
WLE
3 and 2
1
0
相关PDF资料 |
PDF描述 |
|---|---|
| P8216 | Four-Bit Parallel Bidirectional Bus Driver |
| P8226 | Four-Bit Parallel Bidirectional Bus Driver |
| P82284-6 | CPU System Clock Generator |
| D82284-6 | CPU System Clock Generator |
| D82284-6B | CPU System Clock Generator |
相关代理商/技术参数 |
参数描述 |
|---|---|
| P8Z77 DELUXE | 制造商:Asus 功能描述:P8Z77-V Deluxe ATX Motherboard |
| P8Z77 M PRO | 制造商:Asus 功能描述:P8Z77-M Pro MicroATX Motherboard |
| P8Z77 V | 制造商:Asus 功能描述:P8Z77-V ATX Motherboard |
| P8Z77 V PRO | 制造商:Asus 功能描述:P8Z77-V Pro ATX Motherboard |
| P8Z77-V | 制造商:ASUSTeK Computer Inc 功能描述:P8Z77-V ATX Motherboard |
发布紧急采购，3分钟左右您将得到回复。