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参数资料
| 型号： | PC33989DW |
| 厂商： | MOTOROLA INC |
| 元件分类： | 网络接口 |
| 英文描述： | System Basis Chip with High Speed CAN Transceiver |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDSO28 |
| 封装： | PLASTIC, SO-28 |
| 文件页数： | 14/32页 |
| 文件大小： | 676K |
| 代理商： | PC33989DW |
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MC33989
MC33989
Once stop mode is entered the SBC could wake up from the V1 regulator over current detection. In order to allow time for the
MCU to complete the last CPU instruction to allow MCU to enter its low power mode, a deglitcher time of typicall 40us is
implemented.
figure below indicate operation to enter stop mode.
4.8
Reset and watchdogb pins, sofwtare watchdog operations:
4.8.1
Software watchdog (selectable window or time out watchdog)
Software watchdog is used in the SBC normal and stand-by modes for the MCU monitoring. The watchdog can be either
window or time out. This is selectable by SPI (register TIM1, bit WDW). Default is window watchdog. The period for the watchdog
is selectable from SPI from 10 to 350ms (register TIM1, bits WDT0 and WDT1). When the window watchdog is selected, the
closed window is the first part of the selected period, and the open window is the second part of the period. Refer to SPI TIM
register description. The watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the
closed window will generate a reset. Watchdog is cleared through SPI by addressing the TIM1 register.
4.8.2
Reset pin description
A reset output is available in order to reset the microcontroller. Two operation modes for the reset pin are available, mode 1
and mode 2 (refer to table for reset pin operation).
The reset cause when SBC is in mode 1 are:
- Vdd1 falling out of range: if Vdd1 falls below the reset threshold (parameter
Rst-th
), the reset pin is pull low until Vdd1 return
to nominal voltage.
- Power on reset: at device power on or at device wake up from sleep mode, the reset is maintained low until Vdd1 is within its
operation range.
- Watchdog time out: if the watchdog is not cleared the SBC will pull the reset pin low for the duration of the reset duration time
(
parameter: reset-dur).
In mode 2, the reset pin is not activated in case of watchdog time out. Refer to” table for reset pin operation“for mode detail.
For debug purposes at 25°C, reset pin can be shorted to 5V, thanks to its internal limited current drive capability.
4.8.3
Reset and Wdogb operation: mode1 and mode 2 (safe mode):
The watchdog and reset functions have two modes of operation: mode 1 and mode 2 (mode 2 is also called safe mode).
These modes are independent of the SBC modes (Normal, stand-by, sleep, stop). Mode 1 or mode 2 selection is done through
SPI (register MCR, bit SAFE). Default mode after reset is mode 1.
Table below is the reset and watchdog output mode of operation. Two modes (mode 1 and mode 2) are available and are
selectable through the SPI, safe bit. Default operation after reset or power up is mode 1.
In both modes reset is active at device power up and wake up.
In mode 1: Reset is activated in case of Vdd1 fall or watchdog not triggered. Wdogb output is active low as soon as reset goes
low and stays low as long as the watchdog is not properly re-activated by SPI.
In mode 2, safe mode: Reset in not activated in case of Watchdog failure. WDOGB output has same behavior as in mode 1.
The Wdogb output pin is a push pull structure than can drive external component of the application in order for instance to sig-
nal MCU wrong operation.
Events
Mode
WDOGB
output
Reset
output
Device power up
1 or 2 (safe mode)
low to high
low to high
- Vdd1 normal
- Watchdog properly triggered
1
high
high
SPI CSB
SPI Stop / Sleep command
SBC in Normal or Standby mode
SBC in stop mode
no Idd1 over I wake up
SBC in stop mode
with Idd1over I wake up
Idd1 - dglt
Tcsb-stop
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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