- 您现在的位置：买卖IC网 > PDF目录365348 > PC33989DW (MOTOROLA INC) System Basis Chip with High Speed CAN Transceiver PDF资料下载
参数资料
| 型号： | PC33989DW |
| 厂商： | MOTOROLA INC |
| 元件分类： | 网络接口 |
| 英文描述： | System Basis Chip with High Speed CAN Transceiver |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDSO28 |
| 封装： | PLASTIC, SO-28 |
| 文件页数： | 16/32页 |
| 文件大小： | 676K |
| 代理商： | PC33989DW |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
16
MC33989
MC33989
and Tx pins are compatible to ISO11898 specification (IS0 11898: 1993(E)). The control of the CAN physical interface operation
is done through the SPI. CAN modes are independent of the SBC operation modes.
The device can wake up from a CAN message if CAN wake up has been enabled. Refer to CAN module description for detail
of wake up detection.
4.9.5
SPI wake up
The device can wake up by the CSB pin in sleep or stop mode. Wake up is detected by CSB pin transition from low to high
level. In stop mode this correspond to the condition where MCU and SBC are in Stop mode and when the application wake up
event comes through the MCU.
4.9.6
Device power up, SBC wake up
After device or system power up, or after the SBC wakes up from sleep mode, it enters into “reset mode” then into “normal
request mode”.
4.10
Debug mode: hardware and software debug with the SBC.
When the SBC is mounted on the same printed circuit board as the mico controller it supplies, both application software and
SBC dedicated routine must be debugged. Following features allow the user to debug the software by allowing the possibility to
disable the SBC internal software watchdog timer.
4.10.1
Device power up, reset pin connected to Vdd1
At SBC power up, the Vdd1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs
every 350ms. In order to allow software debug and avoid MCU reset the Reset pin can be connected directly to Vdd1 by a jumper.
4.10.2
Debug modes with software watchdog disabled though SPI (Normal Debug, Standby Debug and Stop Debug)
The software watchdog can be disabled through SPI. In order to avoid unwanted watchdog disable and to limit the risk of
disabling the watchdog during SBC normal operation the watchdog disable has to be done with the following sequence:
Step 1) Power down the SBC
Step 2) Power up the SBC (The BATFAIL bit is set, and the SBC enters normal request mode)
Step 3) Write to TIM1 register to allow SBC to enter Normal mode
Step 4) Write to MCR register with data 0000 (this enables the debug mode). (Complete SPI byte: 000 1 0000)
Step 5) Write to MCR register normal debug (0001 x101)
While in debug mode, the SBC can be used without having to clear the W/D on a regular basis to facilitate software and
hardware debug.
Step 6) To leave the debug mode, write 0000 to MCR register.
At step 2, the SBC is in normal request. Step 3, 4 and 5 should be done consecutiveley and withing the 350ms time period of
the normal requets mode. If not, the SBC will go into reset mode and enter again normal request.
When the SBC is in debug mode, and has been set into stop debug or sleep debug, when a wake up occurs the SBC enters
Normal requets mode, for a time period of 350ms. In order to avoid the SBC to generate a reset (enter reset mode) the desired
next debug mode (normal debug or standby debug) should be configured within the 350ms time period of the normal requets
mode (for detail refer to “State machine in debug mode”).
To avoid entering debug mode after a power up, first read BATFAIL bit (MCR read) and write 0000 into MCR.
The graph below illustrates the debug mode enter.
4.10.3
MCU flash programming configuration
In order to allow the possibility to download software into the application memory (MCU EEPROM or Flash) the SBC allows
the following capabilities: The Vdd1 can be forced by an external power supply to 5V and the reset and Wdogb outputs by
external signal sources to zero or 5V and this without damage. This allow for instance to supply the complete application board by
external power supply and to apply the correct signal to reset pins.No function of the SBC are operating.
Due to pass transistor from Vdd1 to Vsup, supplying the device from Vdd1 pin biases the Vsup pin. So Vsup should be left
open of forced to value above 5V. Reset pin is periodically pulled low for “reset dur” time (3.4ms typical) and then pulled to Vdd1
for 350ms typical. During the time reset is low, reset pin sinks 5mA maximum (Ipdw parameter).
For More Information On This Product,
Go to: www.freescale.com
VSup
SPI
MCR(step4)
Batfail
Vdd1
debug mode
MCR (step5)
SPI: read batfail
MCR (step6)
SBC in debug Mode, no W/D
SBC not in debug Mode and W/D on
TIM1(step 3)
F
Freescale Semiconductor, Inc.
n
.
相关PDF资料 |
PDF描述 |
|---|---|
| PC33991R2 | Gauge Driver Integrated Circuit |
| PC33991DH | Gauge Driver Integrated Circuit |
| PC33999EK | 16-Output Switch with SPI and PWM Control |
| PC34710EWR2 | Adjustable Dual Output Switching Power Supply |
| PC34710EW | Adjustable Dual Output Switching Power Supply |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PC33991DH | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Gauge Driver Integrated Circuit |
| PC33991DH/R2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Gauge Driver Integrated Circuit |
| PC33991FS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog Products PC33991FS Fact Sheet |
| PC33991R2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Gauge Driver Integrated Circuit |
| PC33996EK/R2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:16-Output Switch with SPI Control |
发布紧急采购，3分钟左右您将得到回复。