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| 型号： | PC34708VMR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA206 |
| 封装： | 13 X 13 MM, 0.80 MM PITCH, LEAD FREE, MO-275HHAC-1, MAPBGA-206 |
| 文件页数： | 143/200页 |
| 文件大小： | 5160K |
| 代理商： | PC34708VMR2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
47
PC34708
Functional Block Requirements and Behaviors
Power Control Logic Block Description and Application Information
7.2.1.6
User Off Wait
The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered
by a processor request for user off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power
key; upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or
Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off.
The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks.
When expired, the Wait mode is exited for User Off mode or Memory Hold mode depending on warm starts being enabled or not
via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.
7.2.1.7
Memory Hold and User Off (Low Power Off states)
As noted in the User Off Wait description, the system is directed into low power Off states based on a SPI command in response
to an intentional turn off by the end user. The only exit then will be a turn on event. To an end user, the Memory Hold and User
Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external
memory in self-refresh mode (Memory Hold and User Off mode) as well as powering portions of the processor core for state
retention (User Off only). The switcher mode control bits allow selective powering of the buck switchers for optimizing the supply
behavior in the low power Off modes. Linear regulators and most functional blocks are disabled (the RTC module, SPI bits
resetting with RTCPORB, and Turn On event detection are maintained).
By way of example, the following descriptions assume the typical use case where SW1 supplies the processor core(s), SW2 is
applied to the processor’s VCC domain, SW3 supplies the processors internal memory/peripherals, and SW4 supplies the
external memory, and SW5 supplies the I/O rail. The buck switchers are intended for direct connection to the aforementioned
loads.
7.2.1.8
Memory Hold
RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). To
ensure that SW1, SW2, SW3 and SW5 shut off in Memory Hold, appropriate mode settings should be used such as
SW1MHMODE, = SW2MHMODE, = SW3MHMODE, = SW5MHMODE set to = 0 (refer to the mode control description later in
this section). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1.
Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is
set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since
software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot.
No specific timer is running in this mode.
Buck switchers that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when
coming out of MEMHOLD and entering a Warm Boot. The switchers will be reconfigured for their default settings as selected by
the PUMSx pins in the normal time slot that would affect them.
7.2.1.9
User Off
RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected
to the processor’s CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM
is set.
The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1 and/or SW2 and or SW3 supply domains can
be configured for SWxUOMODE=1 to keep them powered through the User Off event. If one of the switchers can be shut down
on in User Off, its mode bits would typically be set to 0.
Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the
processor’s state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used
for very low frequency / low power idling of the core(s), minimizing battery drain, while allowing a rapid recovery from where the
system left off before the USEROFF command.
Upon a turn on event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will
result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with
external memory. No specific timer is running in this mode.
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