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参数资料
| 型号： | PC34708VMR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA206 |
| 封装： | 13 X 13 MM, 0.80 MM PITCH, LEAD FREE, MO-275HHAC-1, MAPBGA-206 |
| 文件页数： | 153/200页 |
| 文件大小： | 5160K |
| 代理商： | PC34708VMR2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
56
PC34708
Functional Block Requirements and Behaviors
Power Control Logic Block Description and Application Information
The LOWBATT detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 50.
7.2.9
Power Saving
7.2.9.1
System Standby
A product may be designed to go into DSM after periods of inactivity, the STANDBY pin is provided for board level control of
timing in and out of such deep sleep modes.
When a product is in DSM, it may be able to reduce the overall platform current by lowering the switcher output voltage, changing
the operating mode pf the switchers or disabling some regulators. This can be obtained by controlling the STANDBY pin. The
configuration of the switcher's/LDO's in standby is pre-programmed through the SPI.
A lower power standby mode can be obtained by setting the ON_STBY_LP SPI bit to a one. With the ON_STBY_LP SPI bit set
and the STANDBY pin asserted a lower power standby will be entered. In the on Standby Low Power mode, the switchers should
all be programmed into PFM mode and the LDO's should be configured to Low Power mode when the STANDBY pin is asserted.
The PLL is disabled in this mode so the mini USB will only be able to detect if a charger is inserted. If an audio device, UART, or
a USB OTG device is attached the PMIC will not be able to auto detect it in Low Power Standby mode. It will require the software
to wake up occasionally to allow the mini-USB to detect if a device is attached by de-asserting the STANDBY pin and waking up
for a period to see if a device is attached and then re-asserting Standby, if a device has not been detected. If a device has been
detected then the software can bring up the appropriate application etc.
Note the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take
into account the programmed input polarity associated with each pin. For simplicity, Standby will generally be referred to as active
high throughout this document, but as defined in Table 51, active low operation can be accommodated. Finally, since STANDBY
pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin
level changes.
The state of the STANDBY pin only has influence in On mode, and are therefore it is ignored during start up and in the Watchdog
phase. This allows the system to power up without concern of the required Standby polarities since software can make
adjustments accordingly as soon as it is running.
A command to transition to one of the low power Off states (User Off or Memory Hold, initiated with USE-ROFFSPI=1) redefines
the power tree configuration based on SWxMODE programming, and has priority over Standby (which also influences the power
tree configuration).
Table 50. VBATTDB Debounce Times
VATTDB[1:0]
Debounce Time
00
0 (default)
01
2 RTC clock cycles
10
4 RTC clock cycles
11
8 RTC clock cycles
Table 51. Standby Pin and Polarity Control
STANDBY (Pin)
STANDBYINV (SPI bit)
STANDBY Control(45)
0
1
0
1
0
Notes
45.
STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby
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