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参数资料
| 型号： | PCA85132U/2DA/Q1,0 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 45/62页 |
| 文件大小： | 0K |
| 描述： | IC LCD DRIVER 32 UNCASED |
| 标准包装： | 600 |
| 显示器类型： | LCD |
| 配置： | 多重 |
| 接口： | I²C |
| 数字或字符： | 任何数字类型 |
| 电流 - 电源： | 60µA |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 95°C |
| 封装/外壳： | 模具 |
| 供应商设备封装： | 模具 |
| 包装： | 散装 |
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NXP Semiconductors
PCA85132
LCD driver for low multiplex rates
the cascade be lost, it is restored by the first PCA85132 to assert SYNC. The timing
relationship between the backplane waveforms and the SYNC signal for the various drive
modes of the PCA85132 are shown in Figure 36 on page 48 .
When using an external clock signal with high frequencies (f clk(ext) > 4 kHz), it is
recommended to have an external pull-up resistor between pin SYNC and pin V DD (see
configuration is used! When using it in a cascaded configuration, care must be taken not
to route the SYNC signal to close to noisy signals.
The contact resistance between the SYNC pads of cascaded devices must be controlled.
If the resistance is too high, the device is not able to synchronize properly. This is
particularly applicable to COG applications. Table 24 shows the limiting values for contact
resistance.
Table 24.
SYNC contact resistance
Number of devices
2
3 to 5
6 to 8
Maximum contact resistance
6000 ?
2200 ?
1200 ?
In the cascaded applications, the OSC pin of the PCA85132 with subaddress 0 is
connected to V SS so that this device uses its internal clock to generate a clock signal at
the CLK pin. The other PCA85132 devices are having the OSC pin connected to V DD ,
meaning that these devices are ready to receive external clock, the signal being provided
by the device with subaddress 0.
If the master is providing the clock signal to the slave devices, care must be taken that the
sending of display enable or disable is received by both, the master and the slaves at the
same time. When the display is disabled, the output from pin CLK is disabled too. The
disconnection of the clock may result in a DC component for the display.
Alternatively, the schematic can be also constructed such that all the devices have OSC
pin connected to V DD and thus an external CLK being provided for the system (all devices
connected to the same external CLK).
A configuration where SYNC is connected but all PCA85132 are using their internal clock
(OSC pin tied to V SS ) should not be used and may lead to display artifacts!
PCA85132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 July 2013
? NXP B.V. 2013. All rights reserved.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PCA85133 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCA85133U/2DA/Q1 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCA85133U/2DA/Q1,0 | 功能描述:IC LCD DRIVER UNIV UNCASED RoHS:是 类别:未定义的类别 >> 其它 系列:* 标准包装:1 系列:* 其它名称:MS305720A |
| PCA85133U/2DB/Q1 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Universal LCD driver for low multiplex rates |
| PCA85133U/2DB/Q1,0 | 功能描述:IC LCD DRIVER UNIV UNCASED RoHS:是 类别:未定义的类别 >> 其它 系列:* 标准包装:1 系列:* 其它名称:MS305720A |
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