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参数资料
| 型号： | PCZ33937AEKR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 运动控制电子 |
| 英文描述： | AC MOTOR CONTROLLER, 0.8 A, PDSO54 |
| 封装： | 0.65 MM PITCH, ROHS COMPLIANT, SOIC-54 |
| 文件页数： | 28/47页 |
| 文件大小： | 750K |
| 代理商： | PCZ33937AEKR2 |
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Analog Integrated Circuit Device Data
34
Freescale Semiconductor
33937
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MODE COMMAND
This command is sent by sending binary 010x xxxx data.
Table 11. Setting Interrupt Masks
Mask:bit
Description
MASK0:0
Over-temperature on any gate drive output generates an interrupt if this bit is set.
MASK0:1
Desaturation event on any output generates an interrupt if this bit is set.
MASK0:2
VLS under-voltage generates an interrupt if this bit is set.
MASK0:3
Over-current Error–if the over-current comparator threshold is exceeded, an interrupt is generated.
MASK1:0
Phase Error–if any Phase comparator output is not at the expected value when an output is command on, an interrupt is
generated. This signal is the XOR of the phase comparator output with the output drive state, and blacked for the duration
of the desaturation blanking interval.
In FULLON mode, this signal is blanked and cannot generate an error.
MASK1:1
Framing Error–if a framing error occurs, an interrupt is generated.
MASK1:2
Write Error after locking.
MASK1:3
Reset Event–If the IC is reset or disabled, an interrupt occurs. Since the IC will always start from a reset condition, this can
be used to test the interrupt mechanism because when the IC comes out of RESET, an interrupt will immediately occur.
Table 12. MODE Command
SPI Data Bits
765
432
10
Write
0
1
0
Desaturation
Fault Mode
0
FULLON
Mode
Lock
Reset
00
Bit 0–Mode Lock is used to enable or disable Mode Lock. If Bit 0 is set, changes to the internal registers are disallowed
to prevent inadvertent changes. This bit cannot be cleared once set. Since the mode Lock mode can only be set, this bit
prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being received. The only
way to clear this bit is to RESET the IC. If an attempt is made to write to a register when Mode Lock is enabled, a Write
Error fault is generated.
Bit 1–FULLON Mode. If this bit is set, programmed deadtime control is disabled, making it is possible to have both high
and Low Side drivers in a phase on simultaneously. This could be useful in special applications such as alternator
regulators, or switched-reluctance motor drive applications. There is no deadtime control in FULLON mode. Input signals
directly control the output stages, synchronized with the internal clock.
This bit is a “0”, after RESET. Until overwritten, the IC operates normally; deadtime control and logic prevents both outputs
from being turned on simultaneously.
Bit 3– Desaturation Fault Mode controls what happen when a desaturation event is detected. When set to “0”, any
desaturation on any channel causes all six output drivers to shutoff. The drivers can only be re-enabled by executing the
CLINT command. When 1, desaturation faults are completely ignored.
Bit 3 controls behavior if a Desaturation, or Phase Error event is detected. The possibilities are:
— 0: Default: When a Desaturation, or Phase Error event is detected on any channel, all channels turn off and generates
an Interrupt, if interrupts are enabled.
— 1: Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked.
Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any further
changes.
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