- 您现在的位置：买卖IC网 > PDF目录98051 > PE33631MLIAA (PEREGRINE SEMICONDUCTOR CORP) PHASE DETECTOR, QCC64 PDF资料下载
参数资料
| 型号： | PE33631MLIAA |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE DETECTOR, QCC64 |
| 封装： | 9 X 9 MM, GREEN, QFN-64 |
| 文件页数： | 2/16页 |
| 文件大小： | 295K |
| 代理商： | PE33631MLIAA |
Advance Information
PE33631
Page 10 of 16
2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0291-01
│ UltraCMOS RFIC Solutions
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (Sdata input), B0 to
B7, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
4. After the falling edge of E_WR, the data provide
control bits as shown in Table 9 on page 10 will
have their bit functionality enabled by asserting
the ENHB input “low”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
“Direct” input “high”.
Counter control bits are set directly at the pins as
shown in Table 7 and Table 8.
Table 7. Secondary Register Programming
Table 8. Auxiliary Register Programming
Table 9. Enhancement Register Programming
Interface
Mode
ENHB
R5
R4
M8
M7 PRE_ENB M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Addr
Direct
1
R5
R4
M8
M7
PRE_ENB
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
X
Serial*
1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11 B12
B13 B14
B15 B16
B17 B18
B19
0
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
Interface
Mode
ENHB
K17 K16 K15
K14 K13
K12 K11 K10
K9
K8
K7
K6
K5
K4
K3
K2
K1
K0
Rsrv
Addr
Direct
1
K17
K16
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
K3
K2
K1
K0
X
Serial*
1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
1
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
Interface
Mode
ENHB
Reserved
fp output
Power
Down
Counter
load
MSEL
output
fc output
LD Disable
Serial*
0
B0
B1
B2
B3
B4
B5
B6
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge
.
MSB (first in)
(last in) LSB
MSB (first in)
相关PDF资料 |
PDF描述 |
|---|---|
| PE33631MLIAA-Z | PHASE DETECTOR, QCC64 |
| PG001M | STEPPER MOTOR CONTROLLER, 0.015 A, PDIP16 |
| PGA308AIDRKR | SPECIALTY ANALOG CIRCUIT, PQCC10 |
| PGA308AIDRKT | SPECIALTY ANALOG CIRCUIT, PQCC10 |
| PGA308AIDGSRG4 | SPECIALTY ANALOG CIRCUIT, PDSO10 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PE3364 | 制造商:PASTERNACK 制造商全称:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY RG223/U BNC FEMALE TO BNC FEMALE |
| PE33641 | 制造商:PASTERNACK 制造商全称:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY RG58C/U SMC PLUG TO SMC PLUG TO SMC PLUG |
| PE33645LF | 制造商:PASTERNACK 制造商全称:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY RG142B/U SMC PLUG RIGHT ANGLE TO SMC PLUG RIGHT ANGLE(LEAD FREE) |
| PE33646 | 制造商:PASTERNACK 制造商全称:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY PE-B150 75 OHM SMC PLUG TO 75 OHM BNC MALE |
| PE33646LF | 制造商:PASTERNACK 制造商全称:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY PE-B150 75 OHM SMC PLUG TO 75 OHM BNC MALE |
发布紧急采购，3分钟左右您将得到回复。