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参数资料
| 型号： | PE33631MLIAA |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE DETECTOR, QCC64 |
| 封装： | 9 X 9 MM, GREEN, QFN-64 |
| 文件页数： | 4/16页 |
| 文件大小： | 295K |
| 代理商： | PE33631MLIAA |
Advance Information
PE33631
Page 12 of 16
2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0291-01
│ UltraCMOS RFIC Solutions
Figure 5. Typical Phase Noise
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_UB,
and PD_DB. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_DB pulses “low”. If the divided reference leads
the divided VCO in phase or frequency (fc leads
fp), PD_UB pulses “low”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
For the UP and DOWN mode, PD_UB and
PD_DB drive an active loop filter which controls
the VCO tune voltage. The phase detector gain is
equal to VDD / 2
п.
PD_UB pulses cause an increase in VCO
frequency and PD_DB pulses cause a decrease in
VCO frequency, for a positive Kv VCO.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_UB
and PD_DB waveforms, which is driven through a
series 2 k
resistor. Connecting Cext to an
external shunt capacitor provides low pass filtering
of this signal. Cext also drives the input of an
internal inverting comparator with an open drain
output. Thus LD is an “AND” function of PD_UB
and PD_DB.
A typical phase noise plot is shown below. “Trace 1” is the smoothed average, and “Trace 2” is the raw data
.
Test Conditions: Fout = 1.9204 GHz in MASH 1-1 mode, Fcomparison = 20 MHz, VDD = 3.3 V, Temp = 25 C, Loop
bandwidth = 50 kHz.
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