FALC
56
PEF 2256 H/E
Operational Description E1
User’s Manual
Hardware Description
199
DS1.1, 2003-10-23
Specific E1 Register Settings
The following is a suggestion for a basic initialization to meet most of the E1
requirements. Depending on different applications and requirement any other
initialization can be used.
E1 Framer Initialization
The selection of the following modes during the basic initialization supports the ETSI
requirements for E-Bit Access, remote alarm and synchronization (please refer also to
FALC
56 driver code of the evaluation system EASY22554 and application notes) and
helps to reduce the software load. They are very helpful especially to meet requirements
as specified in ETS300 011.
Table 49
Register Setting
FMR0.XC0/
FMR0.RC0/
LIM1.DRS
FMR3.CMI
Line Interface Initialization (E1)
Function
The FALC
56 supports requirements for the analog line
interface as well as the digital line interface. For the analog line
interface the codes AMI and HDB3 are supported. For the digital
line interface modes (dual- or single-rail) the FALC
56 supports
AMI, HDB3, CMI (with and without HDB3 precoding) and NRZ.
LOS detection after 176 consecutive “zeros” (fulfills G.775).
LOS recovery after 22 “ones” in the PCD interval (fulfills G.775).
LIM1.RIL(2:0) = 02
H
LOS threshold of 0.6 V (fulfills G.775).
PCD = 0A
H
PCR = 15
H
Table 50
Register Setting
XSP.AXS = 1
Framer Initialization (E1)
Function
ETS300 011 C4.x for instance requires the sending of E-Bits in
TS0 if CRC4 errors have been detected. By programming
XSP.AXS = 1 the submultiframe status is inserted automatically
in the next outgoing multiframe.
If the FALC
56 has reached asynchronous state the E-Bit is
cleared if XSP.EBP = 0 and set if XSP.EBP = 1. ETS 300 011
requires that the E-Bit is set in asynchronous state.
FMR2.AXRA = 1
The transmission of RAI via the line interface is done
automatically by the FALC
56 in case of loss of frame alignment
(FRS0.LFA = 1). If basic framing has been reinstalled RAI is
automatically reset.
XSP.EBP = 1